Method of Forming High-Voltage Transistor with Thin Gate Poly
A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.
1 - 21 . (canceled)
22 . A semiconductor device, comprising:
a non-volatile memory (NVM) cell including a memory gate stack and a select gate stack separated by an inter-gate dielectric disposed in a memory region of a substrate;
a first field-effect transistor (FET) including a high-K metal-gate (HKMG) stack disposed in a peripheral region of the substrate; and
a second FET including a high voltage (HV) gate stack disposed in the peripheral region, wherein top surfaces of the memory gate stack and the select gate stack of the NVM cell and the HV gate stack of the second FET have an approximately same elevation from the substrate.
23 . The semiconductor device of claim 22 , wherein the memory gate stack includes a memory gate disposed over a multi-layer charge-trapping layer, and wherein the select gate stack includes a select gate disposed over a dielectric layer.
24 . The semiconductor device of claim 22 , wherein the HKMG stack of the first FET includes a metal gate disposed over a high-K dielectric layer.
25 . The semiconductor device of claim 22 , wherein the HV gate stack of the second FET includes a polysilicon gate disposed over a HV dielectric layer.
26 . The semiconductor device of claim 22 , wherein the NVM cell includes a split gate memory transistor.
27 . The semiconductor device of claim 22 , wherein the second FET is a HV device that is operational up to approximately 20 V and includes source and drain regions having a depth from 400 Å to 2,000 Å below a surface of the substrate, and wherein the polysilicon gate of the second FET has a gate height from 300 Å to 1,000 Å.
28 . The semiconductor device of claim 23 , wherein a self-aligned silicide (SALICIDE) layer is disposed over at least a portion of the select gate, and wherein the SALICIDE layer is not in direct contact with the inter-gate dielectric.
29 . The semiconductor device of claim 24 , wherein the metal gate of the first FET has a width from 10 nm to 40 nm and a height from 300 Å to 1,000 Å.
30 . The semiconductor device of claim 24 , wherein the metal gate is made of at least one of:
aluminum, copper, titanium, tungsten, and alloys thereof.
31 . The semiconductor device of claim 24 , wherein the high-K dielectric layer includes at least one of:
hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide, and lanthanum oxide.
32 . A memory device, comprising:
a plurality of split gate transistors in a memory region, wherein each split gate transistor includes a memory gate stack disposed adjacent to a select gate stack;
a plurality of logic transistors in a peripheral region, wherein each logic transistor includes a high-K metal-gate (HKMG) stack; and
a plurality of high voltage (HV) transistors in the peripheral region, wherein each HV transistor includes a HV gate stack;
wherein the memory and select gate stacks of the plurality of split gate transistors and the HV gate stack of the plurality of HV transistors have an approximate same height and a commonly planarized top surfaces, and wherein the memory and peripheral regions are disposed within a single substrate.
33 . The memory device of claim 32 , wherein the memory gate stack includes a memory gate disposed over a multi-layer charge-trapping layer, and wherein the select gate stack includes a select gate disposed over a dielectric layer.
34 . The memory device of claim 32 , wherein the HKMG stacks of the plurality of logic transistors each includes a metal gate disposed over a high-K dielectric layer.
35 . The memory device of claim 32 , wherein the HV gate stacks of the plurality of HV transistors each includes a polysilicon gate disposed over a HV dielectric layer.
36 . The memory device of claim 32 , wherein the memory gate stack and select gate stack is separated by an inter-gate dielectric.
37 . The memory device of claim 32 , wherein the plurality of HV transistors are operational up to approximately 20 V and each includes source and drain regions having a depth from 400 Å to 2,000 Å below a surface of the single substrate, and wherein the polysilicon gates each has a gate height from 300 Å to 1,000 Å.
38 . The memory device of claim 36 , wherein a self-aligned silicide (SALICIDE) layer is disposed over at least a portion of each of the select gate, and wherein the SALICIDE layer is not in direct contact with the inter-gate dielectric.
39 . The memory device of claim 34 , wherein the metal gates of the plurality of logic transistors each has a width from 10 nm to 40 nm and a height from 300 Å to 1,000 Å.
40 . The memory device of claim 34 , wherein the metal gates of the plurality of logic transistors are made of at least one of:
aluminum, copper, titanium, tungsten, and alloys thereof.
41 . The memory device of claim 33 , wherein the high-K dielectric layers of the plurality of logic transistors include at least one of:
hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide, and lanthanum oxide.