IP Library Granted Patent US 10,608,858
Granted Patent B2
US 10,608,858 · App. 16/292,991 · Granted Mar 31, 2020

Zero tail and unique word based waveforms for DFT-s OFDM and OFDM

Inventors: Erdem Bala (East Meadow, NY); Mihaela C. Beluri (Jericho, NY); Kyle Jung-Lin Pan (Saint James, NY); Tao Deng (Roslyn, NY); Liangping Ma (San Diego, CA); Yugeswar Deenoo (Chalfont, PA); Ravikumar V. Pragada (Warrington, PA); Alphan Sahin (Westbury, NY)
Assignee: IDAC Holdings, Inc.
H04L27/2627H04L27/2605
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Quick Facts
Patent No.
US 10,608,858
App. No.
16/292,991
Granted
Mar 31, 2020
Kind
B2
Abstract

Methods and systems for operation in a wireless network are provided, the methods including receiving modulated data symbols and zeros in a frequency-domain, and mapping in the frequency-domain the modulated data symbols and zeros in an interleaved manner to sub-carriers within a resource allocation. The methods and systems further include generating a time-domain data signal based on the mapped sub-carriers, and generating a time domain cancellation signal by sign inverting and repeating a predetermined number of time-domain samples at a tail portion of the data signal. The methods and systems further include combining the time-domain data signal and the time domain cancellation signal to generate an exact zero tail data signal such that the exact zero tail data signal has a zero tail length equal to the predetermined number of time-domain samples, and transmitting the exact zero tail data signal.

Claims (36)

1. A wireless transmit/receive unit (WTRU) comprising:

an antenna; and

a processor operatively coupled to the antenna; wherein:

the processor is configured to receive modulated data symbols and zeros in a frequency-domain;

the processor is further configured to map, in the frequency-domain, the modulated data symbols and zeros in an interleaved manner to sub-carriers within a resource allocation;

the processor is further configured to generate a time-domain data signal based on the mapped sub-carriers;

the processor is further configured to generate a time-domain cancellation signal by sign inverting and repeating a predetermined number of time-domain samples at a tail portion of the time-domain data signal;

the processor is further configured to combine the time-domain data signal and the time-domain cancellation signal to generate an exact zero tail data signal, wherein the exact zero tail data signal has a zero tail length equal to the predetermined number of time-domain samples; and

the processor and the antenna are configured to transmit the exact zero tail data signal.

2. The WTRU of claim 1 , wherein the processor is further configured to generate the time-domain cancellation signal by inverting a sign of the time-domain samples and repeating a sequence of the inverted time-domain samples.

3. The WTRU of claim 1 , wherein the processor is further configured to generate the time-domain cancellation signal by inverting a vector comprising the tail time-domain samples and repeating the inverted vector a plurality of times to generate a string of the inverted vectors such that the time-domain cancellation signal comprises the string of the inverted vectors.

4. The WTRU of claim 1 , wherein the processor is further configured to generate the time domain cancellation signal by inverting the time-domain samples, converting the sign inverted time-domain samples into a plurality of frequency-domain symbols, and mapping the plurality of frequency-domain symbols in an interleaved manner to a plurality of allocated sub-carriers.

5. The WTRU of claim 4 , wherein the plurality of frequency-domain symbols are uniformly interleaved over the plurality of allocated sub-carriers.

6. The WTRU of claim 1 , wherein the processor is further configured to generate an exact zero tail data signal by shifting at least one time-domain sample from a tail portion of the exact zero tail data signal to a head portion of the exact zero tail data signal.

7. The WTRU of claim 1 , wherein the exact zero tail data signal comprises a plurality of data blocks each having a zero-tail portion, and wherein the processor is further configured to insert, in the time-domain, a unique word at each zero tail portion of the exact zero tail data signal.

8. The WTRU of claim 1 , wherein the processor is further configured to insert guard bands into the exact zero tail data signal.

9. The WTRU of claim 1 , wherein the processor is further configured to:

sign invert the tail time-domain samples;

convert the tail time-domain samples into an inverted plurality of tail frequency-domain symbols with an Nzt size discrete Fourier transform (DFT);

map the inverted plurality of tail frequency-domain symbols to a plurality of allocated sub-carriers in an interleaved manner such that another plurality of zeros are inserted on

M

N

zt

-

1

 consecutive sub-carriers of the plurality of allocated sub-carriers between each output of the Nzt size DFT, wherein M is a number of the plurality of allocated sub-carriers, Nzt is a number of the selected plurality of tail time-domain samples, and

M

N

zt

 is an integer; and

generate the time domain cancellation signal by converting the mapped inverted plurality of tail frequency-domain symbols into the time-domain such that the time-domain cancellation signal is a replica of the inverted plurality of tail time-domain samples, repeated

M

N

zt

 times.

10. The WTRU of claim 1 , wherein the exact zero tail data signal is an orthogonal frequency-division multiplexing (OFDM) signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2023
From: IDAC HOLDINGS, INC.
To: INTERDIGITAL PATENT HOLDINGS, INC.
Reel/Frame 063089/0085 →
Continuity (3)
Continuation 15777761
Provisional Application 62262649 · Dec 3, 2015
Related Publication 20190199569A1 · Jun 27, 2019