Integrated processor and CDR circuit
A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include processing circuitry configured to control the clock and data recovery circuit. The processing circuitry and the clock and data recovery circuit may be formed on a single substrate.
1. A system, comprising:
a clock and data recovery circuit that includes a voltage controlled oscillator (VCO) and a charge pump coupled to the VCO; and
processing circuitry configured to control the clock and data recovery circuit based on previously stored data that includes a data rate of a previously received data signal from the clock and data recovery circuit, the processing circuitry controlling the clock and data recovery circuit by directing the clock and data recovery circuit to begin at the data rate of the previously received data signal when locking to a data signal;
wherein the clock and data recovery circuit includes a charge pump, wherein the processing circuitry is configured to set rail voltages of the charge pump at a first set of voltages when the clock and data recovery circuit locks to the data signal and to set the rail voltages of the charge pump at a second set of voltages after the clock and data recovery circuit locks to the data signal, wherein a first difference between voltages of the first set of voltages is smaller than a second difference between voltages of the second set of voltages.
2. The system of claim 1 , wherein the clock and data recovery circuit is an analog circuit and the processing circuitry is a digital circuit, wherein transistors in the clock and data recovery circuit and the processing circuitry are formed on a single substrate.
3. The system of claim 1 , wherein the processing circuitry directs the VCO to begin at the data rate of the previously received data signal when locking to the data signal.
4. The system of claim 1 , wherein the processing circuitry is further configured to select the second set of voltages based on a gain of the charge pump after the clock and data recovery circuit locks to the data signal.
5. The system of claim 1 , wherein a first center voltage between the voltages of the first set of voltages is approximately equal to a second center voltage between the voltages of the second set of voltages.
6. The system of claim 1 , wherein the processing circuitry is configured to reduce a gain of the charge pump after the clock and data recovery circuit locks to the data signal.
7. A system, comprising:
a clock and data recovery circuit; and
processing circuitry configured to control the clock and data recovery circuit based on previously stored data that includes a data rate of a previously received data signal from the clock and data recovery circuit, the processing circuitry controlling the clock and data recovery circuit by directing the clock and data recovery circuit to begin at the data rate of the previously received data signal when locking to a data signal,
wherein the clock and data recovery circuit includes a charge pump, wherein the processing circuitry is configured to set rail voltages of the charge pump at a first set of voltages when the clock and data recovery circuit locks to the data signal and to set the rail voltages of the charge pump at a second set of voltages after the clock and data recovery circuit locks to the data signal, wherein a first difference between voltages of the first set of voltages is smaller than a second difference between voltages of the second set of voltages.
8. The system of claim 7 , wherein the clock and data recovery circuit is an analog circuit and the processing circuitry is a digital circuit, wherein transistors in the clock and data recovery circuit and the processing circuitry are formed on a single substrate.
9. The system of claim 7 , wherein the clock and data recovery circuit includes an oscillator, wherein the processing circuitry directs the oscillator to begin at the data rate of the previously received data signal when locking to the data signal.
10. The system of claim 7 , wherein the processing circuitry is further configured to select the second set of voltages based on a gain of the charge pump after the clock and data recovery circuit locks to the data signal.
11. The system of claim 7 , wherein a first center voltage between the voltages of the first set of voltages is approximately equal to a second center voltage between the voltages of the second set of voltages.
12. The system of claim 7 , wherein the processing circuitry is configured to reduce a gain of the charge pump after the clock and data recovery circuit locks to the data signal.
13. A system, comprising:
a clock and data recovery circuit that includes a voltage-controlled oscillator (VCO) and a charge pump coupled to the VCO; and
processing circuitry configured to control the clock and data recovery circuit based on previously stored data received from the clock and data recovery circuit and that includes a data rate of a previously received data signal and a first frequency of the VCO at which the clock and data recovery circuit locked to the previously received data signal, the processing circuitry controlling the clock and data recovery circuit by directing the clock and data recovery circuit to begin at the data rate of the previously received data signal when locking to a data signal, including setting a frequency of the VCO to the first frequency to begin locking to the data signal;
wherein the clock and data recovery circuit is an analog circuit and the processing circuitry is a digital circuit, wherein transistors in the clock and data recovery circuit and the processing circuitry are formed on a single substrate.
14. The system of claim 13 , wherein the clock and data recovery circuit includes a charge pump, wherein the processing circuitry is configured to set rail voltages of the charge pump at a first set of voltages when the clock and data recovery circuit locks to the data signal and to set the rail voltages of the charge pump at a second set of voltages after the clock and data recovery circuit locks to the data signal, wherein a first difference between voltages of the first set of voltages is smaller than a second difference between voltages of the second set of voltages.
15. The system of claim 14 , wherein the processing circuitry is further configured to select the second set of voltages based on a gain of the charge pump after the clock and data recovery circuit locks to the data signal.
16. The system of claim 14 , wherein a first center voltage between the voltages of the first set of voltages is approximately equal to a second center voltage between the voltages of the second set of voltages.
17. The system of claim 14 , wherein the processing circuitry is configured to reduce a gain of the charge pump after the clock and data recovery circuit locks to the data signal.
18. The system of claim 1 , wherein the clock and data recovery circuit further includes a conditioning circuit with an equalizer and a signal detector at an input of the clock and data recovery circuit.
19. The system of claim 1 , wherein the processing circuitry is further configured to enable or disable one or more components of the clock and data recovery circuit during operation to reduce power consumption.
20. The system of claim 13 , wherein the processing circuitry is further configured to enable or disable one or more components of the clock and data recovery circuit during operation to reduce power consumption.