SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes: a substrate; a semiconductor above the substrate; a cell transistor which includes a part formed in the semiconductor; a first silicon nitride layer above the cell transistor; and a second silicon nitride layer above the first silicon nitride layer. The second silicon nitride layer has a characteristic different from that of the first silicon nitride layer.
1 . A semiconductor memory device comprising:
a substrate;
a semiconductor above the substrate;
a cell transistor which includes a part formed in the semiconductor;
a first silicon nitride layer above the cell transistor; and
a second silicon nitride layer above the first silicon nitride layer, the second silicon nitride layer having a characteristic different from that of the first silicon nitride layer.
2 . The device according to claim 1 , wherein:
the second silicon nitride layer has bendability lower than bendability of the first silicon nitride layer.
3 . The device according to claim 2 , wherein:
the second silicon nitride layer has internal stress higher than internal stress of the first silicon nitride layer.
4 . The device according to claim 3 , wherein:
the second silicon nitride layer has density higher than density of the first silicon nitride layer.
5 . The device according to claim 4 , wherein:
the second silicon nitride layer has an amount of N—H couplings smaller than an amount of N—H couplings contained in the first nitride layer.
6 . The device according to claim 5 , wherein:
the first silicon nitride layer has an amount of Si—H couplings larger than an amount of Si—H couplings contained in the second silicon layer.
7 . The device according to claim 6 , wherein:
the second silicon nitride layer is located at a surface of the semiconductor memory device.
8 . The device according to claim 3 , wherein:
the second silicon nitride layer is located at a surface of the semiconductor memory device.
9 . The device according to claim 2 , wherein:
the second silicon nitride layer has density higher than density of the first silicon nitride layer.
10 . The device according to claim 9 , wherein:
the second silicon nitride layer is located at a surface of the semiconductor memory device.
11 . The device according to claim 2 , wherein:
the second silicon nitride layer is located at a surface of the semiconductor memory device.
12 . The device according to claim 1 , wherein:
the second silicon nitride layer has internal stress higher than internal stress of the first silicon nitride layer.
13 . The device according to claim 12 , wherein:
the second silicon nitride layer has density higher than density of the first silicon nitride layer.
14 . The device according to claim 13 , wherein:
the second silicon nitride layer is located at a surface of the semiconductor memory device.
15 . The device according to claim 12 , wherein:
the second silicon nitride layer is located at a surface of the semiconductor memory device.
16 . The device according to claim 1 , wherein:
the second silicon nitride layer has density higher than density of the first silicon nitride layer.
17 . The device according to claim 16 , wherein:
the second silicon nitride layer is located at a surface of the semiconductor memory device.
18 . The device according to claim 1 , wherein:
the first silicon nitride layer has an amount of Si—H couplings larger than an amount of Si—H couplings contained in the second silicon layer.
19 . The device according to claim 18 , wherein:
the second silicon nitride layer is located at a surface of the semiconductor memory device.