Semiconductor memory device and method of manufacturing semiconductor memory device
View Patent ↗According to one embodiment, a semiconductor memory device includes: a stack body having a step structure body with a plurality of wire line layers and a plurality of interlayer insulating layers alternately stacked being set as one step on a substrate; and memory cells arranged three-dimensionally in the stack body, in which the step structure body includes: a plurality of terrace portions configured with the interlayer insulating layers, the plurality of terrace portions having different heights; a plurality of step portions connecting the respective terrace portions in a height direction; insulating layers covering the step portions; and a lead wire line leading out a lowermost wire line layer of a first step onto the terrace portion of a second step being a lower step of the first step.
1. A semiconductor memory device comprising:
a stack body on a substrate, the stack body having a step structure body including a plurality of steps, each step formed with a plurality of sets of stacked layers, each set including a wire line layer and an interlayer insulating layer stacked with each other; and
memory cells arranged three-dimensionally in the stack body, wherein
each of the plurality of steps of the step structure body includes an upper wire line layer and a lower wire line layer and a lead wire line that is formed lower than the lower wire line layer; the upper wire line layer, the lower wire line layer; and the lead wire line being insulated from each other by the interlayer insulating layers,
the step structure body includes:
a plurality of terrace portions configured with the interlayer insulating layers, the plurality of terrace portions positioned at different heights;
a plurality of step portions connecting the respective terrace portions in a height direction; and
insulating layers covering the plurality of step portions, wherein the plurality of steps includes a first step and a second step that is lower than the first step, the lead wire line leads out a lowermost layer of the wire line layers of the first step, which is formed lower than the lower wire line layer of the first step, onto the terrace portion of the second step, and
the lead wire line is thicker than the interlayer insulating layers and thicker than the wire line layers in the step structure body.
2. The semiconductor memory device according to claim 1 , wherein an upper surface of the lead wire line on the second step is higher than an upper surface of the lowermost layer of the wire line layers of the first step.
3. The semiconductor memory device according to claim 1 , wherein an upper surface of at least a portion of the lead wire line on the second step is higher than a lower surface of the lower wire line layer of the first step.
4. The semiconductor memory device according to claim 3 , wherein the lead wire line on the second step and the upper wire line layer of the first step are insulated by the insulating layer covering the step portion of the first step.
5. The semiconductor memory device according to claim 1 , wherein the plurality of wire line layers are respectively connected to the memory cells arranged at the same height.
6. The semiconductor memory device according to claim 5 , wherein the plurality of wire line layers are word lines applying a predetermined voltage to the memory cells.
7. The semiconductor memory device according to claim 6 , wherein the predetermined voltage is applied through the lead wire line connected to each of the wire line layers.
8. The semiconductor memory device according to claim 1 , wherein a contact connected to a wire line arranged on an upper layer of the step structure body is connected to the lead wire line.
9. The semiconductor memory device according to claim 8 , wherein connection depths of the contact with the lead wire lines are different from each other.