INTEGRATED CIRCUITS FOR SECURE DATA STORAGE AND RETRIEVAL
Systems and integrated circuits are provided herein. In one aspect, an integrated circuit comprises: a plurality of connection nodes comprising at least a first and second connection node; a secure IP block and a decrypt IP block coupled to the first and second connection nodes, respectively. The secure IP block is configured to: receive a data object via the first connection node, disassemble the data object into a plurality of data fragments, encrypt the plurality of data fragments, and send the plurality of encrypted data fragments to a plurality of storage locations. The decrypt IP block is configured to: receive an electrical signal indicative of a request to access a data object via the second connection node, retrieve a plurality of encrypted data fragments stored at a plurality of storage locations, decrypt the plurality of encrypted data fragments, and reassemble the decrypted data fragments into the data object.
1 . An integrated circuit comprising:
at least one connection node; and
a secure circuit electrically connected to the at least one connection node, the secure circuit configured to:
receive a data object via the at least one connection node,
disassemble the data object into a plurality of data fragments,
encrypt the plurality of data fragments, and
send the plurality of encrypted data fragments to a plurality of storage locations.
2 . The integrated circuit of claim 1 , wherein the secure circuit comprises a fragmentation block, an encryption block, and a distribution interface block configured to interface with the plurality of storage locations.
3 . The integrated circuit of claim 1 , wherein the secure circuit is configured to individually encrypt each of the data fragments based, in part, on an encryption algorithm.
4 . The integrated circuit of claim 3 , wherein the secure circuit is configured to generate a manifest comprising at least decryption data based on the encryption algorithm.
5 . The integrated circuit of claim 3 , wherein the secure circuit is configured to individually encrypt each of the data fragments upon generating each respective data fragment.
6 . The integrated circuit of claim 1 , wherein the secure circuit is configured to transmit the plurality of encrypted data fragments to the plurality of storage of storage locations based on a data map of a data repository comprising mapping information for storage to the plurality of storage locations.
7 . The integrated circuit of claim 1 , wherein the secure circuit is communicatively coupled to a trusted file manager system comprising the plurality of storage locations.
8 . The integrated circuit of claim 1 , wherein the secure circuit is communicatively coupled to a memory circuit via the at least one connection node, wherein the secure circuit is further configured to receive the data object from the memory circuit.
9 . The integrated circuit of claim 8 , wherein the data object is received as a plurality of pieces in a sequential order based on content of the data object.
10 . The integrated circuit of claim 9 , wherein the secure circuit is configured to disassemble each of the plurality of pieces upon reception of each respective piece.
11 . The integrated circuit of claim 1 , further comprising one or more external pins comprising the at least one connection node, wherein the secure circuit is coupled to a data bus via the one or more external pins.
12 . The integrated circuit of claim 11 , wherein the integrated circuit is an application specific integrated circuit.
13 . The integrated circuit of claim 11 , wherein the integrated circuit is a field programmable gate array.
14 . The integrated circuit of claim 1 , further comprising a processor circuit coupled to the secure circuit via an internal data bus.
15 . An integrated circuit comprising:
at least one connection node; and
a decrypt circuit electrically connected to the at least one connection node, the decrypt circuit configured to:
receive an electrical signal indicative of a request to access a data object via the at least one connection node,
retrieve a plurality of encrypted data fragments stored at a plurality of storage locations,
decrypt the plurality of encrypted data fragments, and
reassemble the decrypted data fragments into the data object.
16 . The integrated circuit of claim 15 , wherein the decrypt circuit comprises an interface block configured to interface with the plurality of storage locations, a decryption block, and a reassembly block.
17 . The integrated circuit of claim 15 , wherein the signal indicative of a request to access a data object comprises an identification of at least one manifest for decrypting a subset of the plurality of data fragments and identifying the subset of the plurality of data fragments.
18 . The integrated circuit of claim 17 , wherein the at least one manifest is encrypted, wherein the decrypt circuit is configured to decrypt the manifest.
19 . The integrated circuit of claim 17 , wherein the decrypt circuit is configured to, based on the at least one manifest, retrieve and decrypt the subset of the plurality data fragments.
20 . The integrated circuit of claim 19 , wherein the decrypt circuit is configured to decrypt each data fragment as each data fragment of the subset of the plurality of data fragments is received.
21 . The integrated circuit of claim 17 , wherein the at least one manifest comprises a data map of a data repository comprising mapping information for retrieving the subset of the plurality of data fragments from the plurality of storage locations.
22 . The integrated circuit of claim 17 , wherein the decrypt circuit is configured reassemble the subset of data fragments based on the at least one manifest.
23 . The integrated circuit of claim 15 , wherein the decrypt circuit is communicatively coupled to a memory circuit via the at least one connection node, wherein the decrypt circuit is further configured to electrically transmit the reassemble decrypted data fragments to the memory circuit.
24 . The integrated circuit of claim 15 , further comprising one or more external pins comprising the at least one connection node, wherein the decrypt circuit is coupled to a data bus via the one or more external pins.
25 . The integrated circuit of claim 24 , wherein the integrated circuit is an application specific integrated circuit.
26 . The integrated circuit of claim 24 , wherein the integrated circuit is a field programmable gate array.
27 . The integrated circuit of claim 15 , further comprising a processor circuit coupled to the decrypt circuit via an internal data bus.
28 . An integrated circuit comprising:
a plurality of connection nodes comprising at least a first connection node and a second connection node;
a secure intellectual property (IP) block coupled to the first connection node, the secure IP block configured to:
receive a data object via the first connection node,
disassemble the data object into a plurality of data fragments,
encrypt the plurality of data fragments, and
send the plurality of encrypted data fragments to a plurality of storage locations; and
a decrypt IP block coupled to the second connection node, the decrypt IP block configured to:
receive an electrical signal indicative of a request to access a data object via the second connection node,
retrieve a plurality of encrypted data fragments stored at a plurality of storage locations,
decrypt the plurality of encrypted data fragments, and
reassemble the decrypted data fragments into the data object.
29 . The integrated circuit of claim 28 , wherein at least one or more of the secure IP block and the decrypt IP block is an asynchronous IP block.
30 . The integrated circuit of claim 28 , wherein the secure IP block and the decrypt IP block are configured to operate independently.
31 . The integrated circuit of claim 28 , wherein the integrated circuit is an application specific integrated circuit.
32 . The integrated circuit of claim 28 , wherein the integrated circuit is a field programmable gate array.
33 . The integrated circuit of claim 15 , further comprising a processor circuit coupled to at least the decrypt IP block and the secure IP block via an internal data bus.