Encoding method and system for memory device including QLC cells
Encoding methods and systems are provided for a memory device including quadruple-level cell (QLC) memory cells. A controller of a memory system includes a constrained encoding device including a first encoder and a second encoder. The first encoder jointly encodes, based on a constrained code, two data bits corresponding to two logical pages, selected from among multiple logical pages. The second encoder independently encodes, based on an error-correction code, the encoded data bits and remaining data bits to generate symbols corresponding to a plurality of program-voltage (PV) levels, the remaining data bits corresponding to two non-selected logical pages among the multiple logical pages.
1. A memory system comprising:
a memory device including quadruple-level cells (QLCs); and
a controller including a constrained encoding device,
wherein the constrained encoding device includes:
a first encoder suitable for jointly encoding, based on a constrained code, two data bits corresponding to two logical pages, selected from among multiple logical pages; and
a second encoder suitable for independently encoding, based on an error-correction code, the encoded data bits and remaining data bits to generate symbols corresponding to a plurality of program-voltage (PV) levels, the remaining data bits corresponding to two non-selected logical pages among the multiple logical pages.
2. The memory system of claim 1 , wherein the two logical pages are selected based on the mapping relationship between the PV levels and the data bits, and certain interference-prone sequences among the symbols.
3. The memory system of claim 2 , wherein the two logical pages include first and third logical pages among the multiple logical pages, and the non-selected logical pages include second and fourth logical pages among the multiple logical pages.
4. The memory system of claim 3 , wherein the first logical page includes the most significant bit (MSB) page,
the second logical page includes the most center significant bit (MCSB) page,
the third logical page includes the least center significant bit (LCSB) page, and
the fourth logical page includes the least significant bit (LSB) page.
5. The memory system of claim 4 , wherein the constrained code includes a code such that bits having the interference-prone sequences are avoided, the bits corresponding to the MSB and LCSB pages.
6. The memory system of claim 5 , wherein a sequence of bits corresponding to the MSB page includes a value of “111”.
7. The memory system of claim 6 , wherein a sequence of bits corresponding to the LCSB page includes a value of “010”.
8. A memory system comprising:
a memory device including quadruple-level cells (QLCs); and
a controller including a constrained encoding device,
wherein the constrained encoding device includes:
a first encoder suitable for jointly encoding, based on a constrained code, first and third data corresponding to first and third logical pages among a plurality of logical pages; and
a second encoder suitable for independently encoding, based on an error-correction code, second and fourth data, and the encoded first and third data to generate symbols corresponding to a plurality of program-voltage (PV) levels, the second and fourth data corresponding to second and fourth logical pages among the plurality of logical pages.
9. The memory system of claim 8 , wherein the controller controls the memory device to program the symbols in the cells.
10. The memory system of claim 8 , wherein the first logical page includes the most significant bit (MSB) page,
the second logical page includes the most center significant bit (MCSB) page,
the third logical page includes the least center significant bit (LCSB) page, and
the fourth logical page includes the least significant bit (LSB) page.
11. The memory system of claim 10 , wherein the constrained code includes a code such that bits having certain sequences are avoided, the bits corresponding to the MSB and LCSB pages, among the symbols.
12. The memory system of claim 11 , wherein a sequence of bits corresponding to the MSB page includes a value of “111”.
13. The memory system of claim 12 , wherein a sequence of bits corresponding to the LCSB page includes a value of “010”.
14. A method for operating a memory system including a memory device including quadruple-level cells (QLCs), the method comprising:
jointly encoding, based on a constrained code, two data bits corresponding to two logical pages, selected from among multiple logical pages; and
independently encoding, based on an error-correction code, the encoded data bits and remaining data bits to generate symbols corresponding to a plurality of program-voltage (PV) levels, the remaining data bits corresponding to two non-selected logical pages among the multiple logical pages.
15. The method of claim 14 , wherein the two logical pages are selected based on the mapping relationship between the PV levels and the data bits, and certain interference-prone sequences among the symbols.
16. The method of claim 15 , wherein the two logical pages include first and third logical pages among the multiple logical pages, and the non-selected logical pages include second and fourth logical pages among the multiple logical pages.
17. The method of claim 16 , wherein the first logical page includes the most significant bit (MSB) page,
the second logical page includes the most center significant bit (MCSB) page,
the third logical page includes the least center significant bit (LCSB) page, and
the fourth logical page includes the least significant bit (LSB) page.
18. The method of claim 17 , wherein the constrained code includes a code such that bits having the interference-prone sequences are avoided, the bits corresponding to the MSB and LCSB pages.
19. The method of claim 18 , wherein a sequence of bits corresponding to the MSB page includes a value of “111”.
20. The method of claim 19 , wherein a sequence of bits corresponding to the LCSB page includes a value of “010”.