Backside Charge Control for FET Integrated Circuits
Semiconductor-on-insulator field effect transistor (FET) integrated circuit (IC) structures and fabrication processes that mitigate or eliminate the problems caused by the secondary parasitic back-channel FET of conventional semiconductor-on-insulator FET IC structures. Embodiments enable full control of the secondary parasitic back-channel FET of semiconductor-on-insulator IC primary FETs. Embodiments include taking partially fabricated ICs made using a process which allows access to the back side of the FET, such as “single layer transfer” process, and then fabricating a conductive aligned supplemental (CAS) gate structure relative to the insulating layer juxtaposed to a primary FET such that a control voltage applied to the CAS gate can regulate the electrical characteristics of the regions of the primary FET adjacent the insulating layer. The IC structures present as a four or five terminal device: source S, drain D, primary gate G, CAS gate, and, optionally, a body contact.
1 - 36 . (canceled)
37 . An integrated circuit structure including:
(a) an insulator layer having a first side and second, opposite side;
(b) two or more series-connected primary field effect transistors (FETs) fabricated on the first side of the insulator layer, each primary FET including a source S, a drain D, a gate insulator, and a gate G; and
(c) a backside conductive layer (BCL) fabricated on the second, opposite side of the insulator layer after the second, opposite side of the insulator layer becomes accessible by application of a backside access process, the BCL including a plurality of fine conductive lines (FCLs) configured as conductive aligned supplemental (CAS) gates, each FCL CAS gate corresponding to one of the two or more primary FETs and being substantially aligned with the gate G of the corresponding primary FET and sized such that little or none of the FCL CAS gate overlaps the source S or drain D of the corresponding primary FET, wherein the source S, the drain D, the FCL CAS gate, and at least the insulator layer function as a field effect transistor.
38 . The invention of claim 37 , wherein the gates G of the two or more primary FETs and the corresponding FCL CAS gates are arrayed in parallel.
39 . The invention of claim 37 , further including at least one conductive interconnect level on the first side of the insulator layer and at least one electrically conductive contact connected to the at least one interconnect level and to at least one FCL CAS gate through the insulator layer.
40 . The invention of claim 39 , wherein the gates G of the two or more primary FETs and the corresponding FCL CAS gates are arrayed in parallel, each FCL CAS gate is coupled to a corresponding electrically conductive contact, and FCL CAS gates are offset along their length with respect to the electrically conductive contacts of adjacent FCL CAS gates.
41 . (canceled)
42 . The invention of claim 39 , wherein the gates G of the two or more primary FETs and the corresponding FCL CAS gates are arrayed in parallel, and at least two FCL CAS gates are connected through a common electrically conductive contact.
43 . The invention of claim 37 , further including at least one lateral capacitor formed by interdigitated FCLs.
44 . (canceled)
45 . The invention of claim 37 , further including at least one inductor formed by one of an FCL planar spiral or an FCL coplanar waveguide.
46 . The invention of claim 37 , further including at least one resistor comprising:
(a) at least one conductive interconnect level on the first side of the insulator layer;
(b) at least one BCL region on the second side of the insulator layer; and
(c) at least one resistive contact electrically connected between the at least one conductive interconnect level and the at least one BCL region through the insulator layer.
47 . An integrated circuit structure including:
(a) an insulator layer having a first side and second, opposite side;
(b) two or more series-connected primary field effect transistors (FETs) fabricated on the first side of the insulator layer, each primary FET including a source S, a drain D, a gate insulator, and a gate G;
(c) at least one conductive interconnect level fabricated on the first side of the insulator layer;
(d) a backside conductive layer (BCL) fabricated on the second, opposite side of the insulator layer after the second, opposite side of the insulator layer becomes accessible by application of a backside access process, the BCL including a plurality of fine conductive lines (FCLs) configured as conductive aligned supplemental (CAS) gates, each FCL CAS gate corresponding to one of the two or more primary FETs and being substantially aligned with the gate G of the corresponding primary FET and sized such that little or none of the FCL CAS gate overlaps the source S or drain D of the corresponding primary FET, wherein the source S, the drain D, the FCL CAS gate, and at least the insulator layer function as a field effect transistor; and
(e) at least one electrically conductive contact connected between the at least one interconnect level and at least two FCL CAS gates through the insulator layer.
48 . The invention of claim 47 , wherein the at least one electrically conductive contact is connected between the at least one interconnect level and the plurality of FCL CAS gates through the insulator layer.
49 . A method for fabricating an integrated circuit structure, including:
(a) fabricating an insulator layer having a first side and second, opposite side;
(b) fabricating two or more series-connected primary field effect transistors (FETs) on the first side of the insulator layer, each primary FET including a source S, a drain D, a gate insulator, and a gate G;
(c) applying a back-side access process to expose the second side of the insulator layer; and
(d) fabricating a backside conductive layer (BCL) on the second, opposite side of the insulator layer, the BCL including a plurality of fine conductive lines (FCLs) configured as conductive aligned supplemental (CAS) gates, each FCL CAS gate corresponding to one of the two or more primary FETs and being substantially aligned with the gate G of the corresponding primary FET and sized such that little or none of the FCL CAS gate overlaps the source S or drain D of the corresponding primary FET, wherein the source S, the drain D, the FCL CAS gate, and at least the insulator layer function as a field effect transistor.
50 . The method of claim 49 , wherein the gates G of the two or more primary FETs and the corresponding FCL CAS gates are arrayed in parallel.
51 . The method of claim 49 , further including fabricating at least one conductive interconnect level on the first side of the insulator layer and fabricating at least one electrically conductive contact connected to the at least one interconnect level and to at least one FCL CAS gate through the insulator layer.
52 . The method of claim 51 , wherein the gates G of the two or more primary FETs and the corresponding FCL CAS gates are arrayed in parallel, each FCL CAS gate is coupled to a corresponding electrically conductive contact, and FCL CAS gates are offset along their length with respect to the electrically conductive contacts of adjacent FCL CAS gates.
53 . (canceled)
54 . The method of claim 51 , wherein the gates G of the two or more primary FETs and the corresponding FCL CAS gates are arrayed in parallel, and at least two FCL CAS gates are connected through a common electrically conductive contact.
55 . The method of claim 49 , further including fabricating at least one lateral capacitor formed by interdigitated FCLs.
56 . (canceled)
57 . The method of claim 49 , further including fabricating at least one inductor formed by one of an FCL planar spiral or an FCL coplanar waveguide.
58 . The method of claim 49 , further including fabricating at least one resistor, including:
(a) fabricating at least one conductive interconnect level on the first side of the insulator layer;
(b) fabricating at least one BCL region on the second side of the insulator layer; and
(c) fabricating at least one resistive contact electrically connected between the at least one conductive interconnect level and the at least one BCL region through the insulator layer.
59 . A method of fabricating an integrated circuit structure, including:
(a) fabricating an insulator layer having a first side and second, opposite side;
(b) fabricating two or more series-connected primary field effect transistors (FETs) on the first side of the insulator layer, each primary FET including a source S, a drain D, a gate insulator, and a gate G;
(c) fabricating at least one conductive interconnect level on the first side of the insulator layer;
(d) applying a back-side access process to expose the second side of the insulator layer;
(e) fabricating a backside conductive layer (BCL) on the second, opposite side of the insulator layer, the BCL including a plurality of fine conductive lines (FCLs) configured as conductive aligned supplemental (CAS) gates, each FCL CAS gate corresponding to one of the two or more primary FETs and being substantially aligned with the gate G of the corresponding primary FET and sized such that little or none of the FCL CAS gate overlaps the source S or drain D of the corresponding primary FET, wherein the source S, the drain D, the FCL CAS gate, and at least the insulator layer function as a field effect transistor; and
(f) fabricating at least one electrically conductive contact in electrical connection between the at least one interconnect level and at least two FCL CAS gates through the insulator layer.
60 . The invention of claim 59 , wherein the at least one electrically conductive contact is connected between the at least one interconnect level and the plurality of FCL CAS gates through the insulator layer.