According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.
1. A memory system comprising:
a semiconductor memory including a first word line, a second word line, a third word line, and a fourth word line arranged in order above a semiconductor substrate, and including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell coupled to the first to fourth word lines, respectively; and
a controller configured to issue a first instruction to determine a threshold distribution of memory cells, and a second instruction to read data from a memory cell using a read voltage based on the threshold distribution,
wherein the controller is further configured to execute:
a first operation, by selecting the first word line and issuing the first instruction, to obtain a first read voltage based on a threshold distribution of the first memory cell;
a second operation, by selecting the second word line and issuing the second instruction designating a voltage based on the first read voltage as the read voltage, to read data from the second memory cell;
a third operation, by selecting the third word line and issuing the first instruction, to obtain a second read voltage based on a threshold distribution of the third memory cell; and
a fourth operation, by selecting the fourth word line and issuing the second instruction designating a voltage based on the second read voltage as the read voltage, to read data from the fourth memory cell.
2. The system according to claim 1 , wherein the semiconductor memory further includes a fifth word line and a sixth word line, and includes a fifth memory cell and a sixth memory cell coupled to the fifth and sixth word lines, respectively,
the first word line is between the second word line and the fifth word line,
the third word line is between the fourth word line and the sixth word line, and
the controller is further configured to execute, after the first operation:
a fifth operation, by selecting the fifth word line and issuing the second instruction designating a voltage based on the first read voltage as the read voltage, to read data from the fifth memory cell; and
the second operation after the fifth operation.
3. The system according to claim 1 , wherein the semiconductor memory further includes:
a first selection gate line;
a first selection transistor coupled to the first selection gate line; and
a first bit line,
wherein the first to fourth memory cells are coupled in series, and are coupled to the first bit line via the first selection transistor.
4. The system according to claim 3 , wherein the semiconductor memory further includes:
a fifth memory cell, a sixth memory cell, a seventh memory cell, and an eighth memory cell coupled to the first to fourth word lines, respectively;
a second selection gate line; and
a second selection transistor coupled to the second selection gate line,
wherein the fifth to eighth memory cells are coupled in series, and are coupled to the first bit line via the second selection transistor, and
the controller is further configured to execute:
a fifth operation, by selecting the first word line and issuing the second instruction designating a voltage based on the first read voltage as the read voltage, to read data from the fifth memory cell;
a sixth operation, by selecting the second word line and issuing the second instruction designating a voltage based on the first read voltage as the read voltage, to read data from the sixth memory cell;
a seventh operation, by selecting the third word line and issuing the second instruction designating a voltage based on the second read voltage as the read voltage, to read data from the seventh memory cell; and
an eighth operation, by selecting the fourth word line and issuing the second instruction designating a voltage based on the second read voltage as the read voltage, to read data from the eighth memory cell.
5. The system according to claim 1 , wherein the semiconductor memory includes a first block including the first to fourth memory cells, and a second block, wherein each of the first block and the second block is a unit of data erasing,
when one of the second operation and the fourth operation fails to read data, the controller issues a third instruction, and
in response to the third instruction, the semiconductor memory copies the data in the first block to the second block.
6. The system according to claim 1 , wherein the semiconductor memory further includes a fifth word line, and a fifth memory cell coupled to the fifth word line,
wherein the controller is further configured to execute a fifth operation, by selecting the fifth word line and issuing the first instruction, to obtain a third read voltage based on a threshold distribution of the fifth memory cell, and
in the second operation, a voltage based on the first read voltage and the third read voltage is designated as the read voltage.
7. The system according to claim 6 , wherein the semiconductor memory further includes:
a first selection gate line and a second selection gate line;
a first selection transistor and a second selection transistor coupled to the first and second selection gate lines, respectively; and
a first bit line,
wherein the first to fourth memory cells are coupled in series, and are coupled to the first bit line via the first selection transistor,
the fifth memory cell is coupled to the first bit line via the second selection transistor, and
the first word line is coupled to the fifth word line.
8. The system according to claim 6 , wherein the fifth word line is located between the first word line and the second word line, and
the first to fifth memory cells are coupled in series.
9. A memory system comprising:
a semiconductor memory including a first word line, a second word line, and a third word line arranged in order above a semiconductor substrate, and including a first memory cell, a second memory cell, and a third memory cell coupled to the first to third word lines, respectively; and
a controller configured to issue a first instruction to determine a threshold distribution of memory cells, and a second instruction to read data from a memory cell using a read voltage based on the threshold distribution,
wherein the controller is further configured to execute:
a first operation, by selecting the first word line and issuing the first instruction, to obtain a first read voltage based on a threshold distribution of the first memory cell;
a second operation, by selecting the third word line and issuing the first instruction, to obtain a second read voltage based on a threshold distribution of the third memory cell; and
a third operation, by selecting the second word line and issuing the second instruction designating a third read voltage as the read voltage, to read data from the second memory cell, and
wherein the third read voltage is between the first read voltage and the second read voltage.
10. The system according to claim 9 , wherein when reading data from the first to third memory cells, the controller designates shift amounts of voltages to be applied to the first to third word lines by a set feature command, and
a shift amount for the second word line is between a shift amount for the first word line and a shift amount for the third word line.
11. The system according to claim 9 , wherein the controller calculates the third read voltage based on the first read voltage and the second read voltage.