IP Library Granted Patent US 11,362,764
Granted Patent B2
US 11,362,764 · App. 16/314,949 · Granted Jun 14, 2022

Base station apparatus, terminal apparatus, communication method, and integrated circuit

Inventors: Kazunari Yokomakura (Sakai, JP); Shohei Yamada (Sakai, JP); Hidekazu Tsuboi (Sakai, JP); Hiroki Takahashi (Sakai, JP); Tatsushi Aiba (Sakai, JP)
Assignees: FG Innovation Company Limited; Sharp Kabushiki Kaisha
H04L1/0057H03M13/09H04L1/00H04L27/01H04L27/26H04L27/2602H04W80/02
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,362,764
App. No.
16/314,949
Granted
Jun 14, 2022
Kind
B2
Abstract

Provided is a coding unit to determine the number of code block groups, divide an input bit sequence to code block segmentation into code block groups of the number of the code block groups, determine the number of code blocks for each of the code block groups, divide each of the code block groups into code blocks of the number of the code blocks, and apply channel coding to each of the code blocks.

Claims (23)

1. A terminal device comprising:

determination circuitry configured to determine a determined number of code block groups, wherein the determined number of code block groups is determined based in part on transport block size;

code block segmentation circuitry configured to segment the input bit sequence into a plurality of code blocks based on a parameter related to a maximum size of each code block; and

encoding circuitry configured to perform channel encoding of each of the plurality of code blocks based on low density parity check (LDPC) coding, wherein the determined number of code block groups is determined based in part on the maximum size of each code block, wherein a cyclic redundancy check parity bit is attached to each of the code blocks of the code block groups, and wherein the encoding circuitry is configured to report a hybrid automatic repeat request (HARQ) information bit for each code block group indicative of whether all of the code blocks of each code block group were correctly received.

2. The terminal device of claim 1 , wherein the code block segmentation circuitry is configured to attach a cyclic redundancy check to the input bit sequence.

3. The terminal device of claim 1 , wherein each cyclic redundancy check provides error detection to the code block to which that cyclic redundancy check is attached.

4. A method for a terminal device, the method comprising:

determining, by determination circuitry, a determined number of code block groups, wherein the determined number of code block groups is determined based in part on transport block size;

segmenting, by code block segmentation circuitry, the input bit sequence into a plurality of code blocks based on a parameter related to a maximum size of each code block;

performing, by encoding circuitry, channel encoding of each of the plurality of code blocks based on low density parity check (LDPC) coding, wherein the determined number of code block groups is determined based in part on the maximum size of each code block, wherein a cyclic redundancy check parity bit is attached to each of the code blocks of the code block groups; and

reporting, by the encoding circuitry, a hybrid automatic repeat request (HARQ) information bit for each code block group indicative of whether all of the code blocks of each code block group were correctly received.

5. The method of claim 4 , wherein the code block segmentation circuitry attaches a cyclic redundancy check to the input bit sequence.

6. A base station device comprising:

determination circuitry configured to determine a determined number of code block groups, wherein the determined number of code block groups is determined based in part on transport block size;

code block segmentation circuitry configured to segment the input bit sequence into a plurality of code blocks based on a parameter related to a maximum size of each code block; and

encoding circuitry configured to perform channel encoding of each of the plurality of code blocks based on low density parity check (LDPC) coding, wherein the determined number of code block groups is determined based in part on the maximum size of each code block, wherein a cyclic redundancy check parity bit is attached to each of the code blocks of the code block groups, and wherein the encoding circuitry is configured to report a hybrid automatic repeat request (HARQ) information bit for each code block group indicative of whether all of the code blocks of each code block group were correctly received.

7. The base station device of claim 6 , wherein the code block segmentation circuitry is configured to attach a cyclic redundancy check to the input bit sequence.

8. A method for a base station, the method comprising:

determining, by determination circuitry, a determined number of code block groups, wherein the determined number of code block groups is determined based in part on transport block size;

segmenting, by code block segmentation circuitry, the input bit sequence into a plurality of code blocks based on a parameter related to a maximum size of each code block; and

performing, by encoding circuitry, channel encoding of each of the plurality of code blocks based on low density parity check (LDPC) coding, wherein the determined number of code block groups is determined based in part on the maximum size of each code block, wherein a cyclic redundancy check parity bit is attached to each of the code blocks of the code block groups; and

reporting, by the encoding circuitry, a hybrid automatic repeat request (HARQ) information bit for each code block group indicative of whether all of the code blocks of each code block group were correctly received.

9. The method of claim 8 , wherein the code block segmentation circuitry attaches a cyclic redundancy check to the input bit sequence.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2024
From: SHARP KABUSHIKI KAISHA; FG INNOVATION COMPANY LIMITED
To: SHARP KABUSHIKI KAISHA
Reel/Frame 069039/0212 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2019
From: SHARP KABUSHIKI KAISHA
To: SHARP KABUSHIKI KAISHA; FG INNOVATION COMPANY LIMITED
Reel/Frame 049235/0738 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2019
From: YOKOMAKURA, KAZUNARI; YAMADA, SHOHEI; TSUBOI, HIDEKAZU; TAKAHASHI, HIROKI; AIBA, TATSUSHI
To: SHARP KABUSHIKI KAISHA
Reel/Frame 048981/0488 →