IP Library Granted Patent US 11,422,955
Granted Patent B2
US 11,422,955 · App. 16/315,058 · Granted Aug 23, 2022

Electronic device

Inventors: Seung-hun Park (Suwon-si, KR); Seob Cho (Suwon-si, KR); Keon-young Seo (Suwon-si, KR); Nam-jin Kim (Suwon-si, KR); Kwang-Rae Jo (Suwon-si, KR); Jung-Soo Park (Suwon-si, KR); Youn-Jae Kim (Suwon-si, KR); Jeong-Nam Cheon (Suwon-si, KR)
Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
G06F13/1668G06F3/0604G06F3/0659G06F3/0673G06F11/0727G06F11/0751G06F11/0793H05K1/181H05K2201/10159
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Quick Facts
Patent No.
US 11,422,955
App. No.
16/315,058
Granted
Aug 23, 2022
Kind
B2
Abstract

An electronic device is disclosed. The electronic device comprises a circuit board, a memory part comprising a plurality of first memory chips mounted on the circuit board, a socket part comprising a plurality of terminals electrically connected to a memory module which comprises a plurality of second memory chips, a memory controller for controlling the operation of the plurality of first memory chips and, when the memory module is connected to the socket part, controlling the operation of the plurality of first memory chips and the plurality of second memory chips, a conductive pattern comprising a control line which sequentially connects, from the memory controller, one or more of the plurality of terminals on the socket part and the plurality of first memory chips, and a capacitive element connected to the control line at a preset position between the one or more terminals on the socket part and the memory controller.

Claims (39)

1. An electronic device comprising:

a circuit board;

a memory part including a plurality of first memory chips mounted on the circuit board;

a socket part including a plurality of terminals to electrically connect to a memory module including a plurality of second memory chips;

a memory controller to control an operation of the plurality of first memory chips, and to control operations of the plurality of first memory chips and the plurality of second memory chips when the memory module is connected to the socket part;

a conductive pattern including a control line that connects at least one of a plurality of terminals of the socket part electrically connectable to the memory module with the plurality of first memory chips, sequentially from the memory controller; and

a capacitive element connected to the control line at a predetermined position between at least one terminal of the socket part and the memory controller,

wherein the capacitive element is connected to the control line between at least one terminal of the socket part and the memory controller at a distance corresponding to an odd multiply of an operating frequency of a control signal which is transmitted and received through the control line from at least one terminal of the socket part.

2. The electronic device as claimed in claim 1 , wherein the capacitive element is connected to the control line at a distance corresponding to 9 th multiplication of the operating frequency of the control signal from at least one terminal of the socket part.

3. The electronic device as claimed in claim 1 , wherein the capacitive element is connected to the control line between at least one terminal of the socket part and the memory controller so as to have a distance satisfying an Equation:

Distance

from

Socket

=

C

4

*

F

*

n

from at least one terminal of the socket part, and

wherein C is a speed of light, F is the operating frequency of the control signal, and n is a natural number of an odd multiply.

4. The electronic device as claimed in claim 3 , wherein the capacitive element is connected to the control line between at least one terminal of the socket part and the memory controller within ±10% of the distance satisfying the Equation.

5. The electronic device as claimed in claim 1 , wherein the capacitive element has a capacitance of 0.1 pF to 18 pF.

6. The electronic device as claimed in claim 1 , wherein the control line transmits a control signal for controlling the plurality of first memory chips, or the plurality of first memory chips and the plurality of second memory chips.

7. The electronic device as claimed in claim 6 , wherein the control signal includes at least one signal of a nRAS signal, a nCAS signal, a nWE signal, a bank address group signal, and an address group signal.

8. The electronic device as claimed in claim 6 , wherein the control signal is sequentially provided to the plurality of memory chips, respectively.

9. The electronic device as claimed in claim 6 , wherein when an error occurs in at least one of the plurality of first memory chips or the plurality of second memory chips, the memory controller varies an operating frequency of a predetermined control signal to a slower operating frequency and outputs the slower operating frequency to the control line.

10. The electronic device as claimed in claim 1 , wherein the conductive pattern includes a plurality of control lines,

the number of the capacitive elements is plural, and

the plurality of capacitive elements is connected to the plurality of control lines, respectively.

11. The electronic device as claimed in claim 1 , further comprising a pull-up resistor connected to the control line between at least one terminal of the socket part and the memory part.

12. The electronic device as claimed in claim 1 , wherein when the memory module is connected to the socket part, the memory controller acquires an operating frequency information of the connected memory module, and controls the operations of the plurality of first memory chips and the plurality of second memory chips based on information on the acquired operating frequency.

13. The electronic device as claimed in claim 12 , wherein when the operating frequency of the connected memory module is different from the operating frequency of the memory part, the memory controller controls the operations of the plurality of first memory chips and the plurality of second memory chips based on a slower operating frequency.

14. The electronic device as claimed in claim 12 , further comprising a display to display notification information when the operating frequency of the connected memory module is different from the operating frequency of the memory part.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2019
From: HP PRINTING KOREA CO., LTD.
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 050743/0251 →
CHANGE OF LEGAL ENTITY EFFECTIVE AUG. 31, 2018 Recorded Oct 16, 2019
From: HP PRINTING KOREA CO., LTD.
To: HP PRINTING KOREA CO., LTD.
Reel/Frame 050938/0139 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2019
From: HP PRINTING KOREA CO., LTD.
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 049521/0323 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2019
From: PARK, SEUNG-HUN; CHO, SEOB; SEO, KEON-YOUNG; KIM, NAM-JIN; JO, KWANG-RAE; PARK, JUNG-SOO; KIM, YOUN-JAE; CHEON, JEONG-NAM
To: HP PRINTING KOREA CO., LTD.
Reel/Frame 049524/0001 →
Priority Claims (1)
KR 10-2016-0084292 · Jul 4, 2016 · national
Continuity (1)
Related Publication 20200183863A1 · Jun 11, 2020