Transmission apparatus, reception apparatus, communication method, and integrated circuit
An apparatus includes a coding unit configured to divide a transport block into one or more code blocks and generate coded bit(s) by coding the one or more code blocks, and a transmitter configured to transmit the coded bit(s) by using a channel, wherein multiplex bit(s) are given based on at least coupling of the coded bit(s) generated by coding of the one or more code blocks, the coding unit maps the multiplex bit(s) to a matrix in a first-axis prioritized manner and reads the multiplex bit(s) from the matrix in the first-axis prioritized manner or in a second-axis prioritized manner, and whether the first axis or the second axis is prioritized in a case that the multiplex bit(s) are read from the matrix is given based on at least the number of OFDM symbols of the channel.
1. A terminal device comprising:
encoding circuitry configured to and/or programmed to
divide a first sequence that is a first transport block with a first Cyclic Redundancy Check (CRC) into a plurality of first code blocks,
generate first coded bits by applying a first error correcting code to the plurality of first code blocks,
divide a second sequence that is a second transport block with a second CRC into a plurality of second code blocks, and
generate second coded bits by applying a second error correcting code to the plurality of second code blocks, and
transmitting circuitry configured to and/or programmed to
transmit a third sequence on a first Physical Uplink Shared Channel (PUSCH), and
transmit a fourth sequence on a second PUSCH, wherein
first multiplexed bits are given at least based on concatenation of the first coded bits generated by each of the plurality of first code blocks,
second multiplexed bits are given at least based on concatenation of the second coded bits generated by each of the plurality of second code blocks,
the first error correcting code is a Turbo code,
the third sequence is given by mapping the first multiplexed bits to a first matrix in a first-axis prioritized manner and by reading out from the first matrix in a second-axis prioritized manner, and
the second error correcting code is a Low Density Parity Check (LDPC) code and the fourth sequence is given by mapping the second multiplexed bits to a second matrix in the first-axis prioritized manner and by reading out from the second matrix in the first-axis prioritized manner.
2. A method of a terminal device, the method comprising:
dividing a first sequence that is a first transport block with a first Cyclic Redundancy Check (CRC) into a plurality of first code blocks,
generating first coded bits by applying a first error correcting code to the plurality of first code blocks,
dividing a second sequence that is a second transport block with a second CRC into a plurality of second code blocks, and
generating second coded bits by applying a second error correcting code to the plurality of second code blocks, and
transmitting a third sequence on a first Physical Uplink Shared Channel (PUSCH), and
transmitting a fourth sequence on a second PUSCH, wherein
first multiplexed bits are given at least based on concatenation of the first coded bits generated by each of the plurality of first code blocks,
second multiplexed bits are given at least based on concatenation of the second coded bits generated by each of the plurality of second code blocks,
the first error correcting code is a Turbo code,
the third sequence is given by mapping the first multiplexed bits to a first matrix in a first-axis prioritized manner and by reading out from the first matrix in a second-axis prioritized manner, and
the second error correcting code is a Low Density Parity Check (LDPC) code and the fourth sequence is given by mapping the second multiplexed bits to a second matrix in the first-axis prioritized manner and by reading out from the second matrix in the first-axis prioritized manner.