IP Library Granted Patent US 11,455,447
Granted Patent B2
US 11,455,447 · App. 16/321,929 · Granted Sep 27, 2022

Activity coverage assessment of circuit designs under test stimuli

Inventor: Stephen Kenneth Sunter (Nepean, CA)
Assignee: Siemens Industry Software Inc.
G06F30/3308G01R31/318357G06F30/33G06F30/367G06F30/38
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,455,447
App. No.
16/321,929
Granted
Sep 27, 2022
Kind
B2
Abstract

Aspects of the disclosed technology relate to techniques of activity coverage assessment. Transistor-level circuit simulation is performed for a circuit design under a set of test stimuli, which determines values of one or more electrical properties for each of circuit elements of interest in the circuit design. The one or more electrical properties are selected based on information of the each of circuit elements of interest, which comprises what circuit element type the each of circuit elements of interest belongs to. Based on the values of the one or more electrical properties, activity coverage information comprising information about which circuit elements in the circuit elements of interest are active or inactive under the set of test stimuli is determined.

Claims (52)

1. A method, executed by at least one processor of a computer, comprising:

receiving information of a circuit design;

performing transistor-level circuit simulation of the circuit design under a set of test stimuli, the transistor-level circuit simulation determining directly or indirectly values of one or more electrical properties for each of circuit elements of interest in the circuit design, the one or more electrical properties being selected based on information of the each of circuit elements of interest, the information of the each of circuit elements of interest comprising what circuit element type the each of circuit elements of interest belongs to;

determining statistical values of the one or more electrical properties based on the values of the one or more electrical properties; and

storing the statistical values of the one or more electrical properties, wherein the statistical values of the one or more electrical properties are used to determine activity coverage information, the activity coverage information comprising information about which circuit elements in the circuit elements of interest are active or inactive under the set of test stimuli.

2. The method recited in claim 1 , wherein the activity coverage information is determined further based on likelihood of occurrence for potential defects associated with the each of circuit elements of interest.

3. The method recited in claim 1 , further comprising:

comparing the statistical values of the one or more electrical properties with predetermined threshold values of the one or more electrical properties to determine the activity coverage information.

4. The method recited in claim 1 , further comprising:

comparing the statistical values of the one or more electrical properties with predetermined threshold values of the one or more electrical properties, wherein the results of the comparing for each of the circuit elements of interest that has only one electrical property in the one or more electrical properties are used to determine whether the each of the circuit elements of interest that has only one electrical property in the one or more electrical properties is active or not; and

determining whether each of the circuit elements of interest that has two or more electrical properties in the one or more electrical properties is active or not based on a logical combination of the results of the comparing for the each of the circuit elements of interest that has two or more electrical properties in the one or more electrical properties.

5. The method recited in claim 1 , wherein the one or more electrical properties are selected further based on information of potential defects associated with the each of circuit elements of interest.

6. The method recited in claim 5 , wherein the information of potential defects associated with the each of circuit elements of interest is determined based at least in part on layout information, properties of the each of circuit elements of interest, or any combination thereof.

7. The method recited in claim 1 , wherein the information of the each of circuit elements of interest further comprises whether the each of circuit elements of interest is a design-intent circuit element or a parasitic circuit element, whether the each of circuit elements of interest is a basic circuit element or a complex circuit element, signal frequencies applied to the each of circuit elements of interest, or any combination thereof.

8. The method recited in claim 1 , wherein the circuit elements of interest comprise all of or a subset of design-intent circuit elements of the circuit design.

9. The method recited in claim 8 , wherein the subset of design-intent circuit elements of the circuit design is randomly selected.

10. The method recited in claim 1 , wherein the activity coverage information comprises information about what percentage of the circuit elements of interest are active.

11. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:

receiving information of a circuit design;

performing transistor-level circuit simulation of the circuit design under a set of test stimuli, the transistor-level circuit simulation determining directly or indirectly values of one or more electrical properties for each of circuit elements of interest in the circuit design, the one or more electrical properties being selected based on information of the each of circuit elements of interest, the information of the each of circuit elements of interest comprising what circuit element type the each of circuit elements of interest belongs to;

determining statistical values of the one or more electrical properties based on the values of the one or more electrical properties; and

storing the statistical values of the one or more electrical properties, wherein the statistical values of the one or more electrical properties are used to determine activity coverage information, the activity coverage information comprising information about which circuit elements in the circuit elements of interest are active or inactive under the set of test stimuli.

12. The one or more non-transitory computer-readable media recited in claim 11 , wherein the activity coverage information is determined further based on likelihood of occurrence for potential defects associated with the each of circuit elements of interest.

13. The one or more non-transitory computer-readable media recited in claim 11 , wherein the method further comprises:

comparing the statistical values of the one or more electrical properties with predetermined threshold values of the one or more electrical properties to determine the activity coverage information.

14. The one or more non-transitory computer-readable media recited in claim 11 , wherein the method further comprises:

comparing the statistical values of the one or more electrical properties with predetermined threshold values of the one or more electrical properties, wherein the results of the comparing for each of the circuit elements of interest that has only one electrical property in the one or more electrical properties are used to determine whether the each of the circuit elements of interest that has only one electrical property in the one or more electrical properties is active or not; and

determining whether each of the circuit elements of interest that has two or more electrical properties in the one or more electrical properties is active or not based on a logical combination of the results of the comparing for the each of the circuit elements of interest that has two or more electrical properties in the one or more electrical properties.

15. The one or more non-transitory computer-readable media recited in claim 11 , wherein the one or more electrical properties are selected further based on information of potential defects associated with the each of circuit elements of interest.

16. The one or more non-transitory computer-readable media recited in claim 15 , wherein the information of potential defects associated with the each of circuit elements of interest is determined based at least in part on layout information, properties of the each of circuit elements of interest, or any combination thereof.

17. The one or more non-transitory computer-readable media recited in claim 11 , wherein the information of the each of circuit elements of interest further comprises whether the each of circuit elements of interest is a design-intent circuit element or a parasitic circuit element, whether the each of circuit elements of interest is a basic circuit element or a complex circuit element, signal frequencies applied to the each of circuit elements of interest, or any combination thereof.

18. The one or more non-transitory computer-readable media recited in claim 11 , wherein the circuit elements of interest comprise all of or a subset of design-intent circuit elements of the circuit design.

19. The one or more non-transitory computer-readable media recited in claim 18 , wherein the subset of design-intent circuit elements of the circuit design is randomly selected.

20. The one or more non-transitory computer-readable media recited in claim 11 , wherein the activity coverage information comprises information about what percentage of the circuit elements of interest are active.

21. A system, comprising:

one or more processors, the one or more processors programmed to perform a method, the method comprising:

receiving information of a circuit design;

performing transistor-level circuit simulation of the circuit design under a set of test stimuli, the transistor-level circuit simulation determining directly or indirectly values of one or more electrical properties for each of circuit elements of interest in the circuit design, the one or more electrical properties being selected based on information of the each of circuit elements of interest, the information of the each of circuit elements of interest comprising what circuit element type the each of circuit elements of interest belongs to;

determining statistical values of the one or more electrical properties based on the values of the one or more electrical properties; and

storing the statistical values of the one or more electrical properties, wherein the statistical values of the one or more electrical properties are used to determine activity coverage information, the activity coverage information comprising information about which circuit elements in the circuit elements of interest are active or inactive under the set of test stimuli.

22. The system recited in claim 21 , wherein the activity coverage information is determined further based on likelihood of occurrence for potential defects associated with the each of circuit elements of interest.

23. The system recited in claim 21 , wherein the method further comprises:

comparing the statistical values of the one or more electrical properties with predetermined threshold values of the one or more electrical properties to determine the activity coverage information.

24. The system recited in claim 21 , wherein the method further comprises:

comparing the statistical values of the one or more electrical properties with predetermined threshold values of the one or more electrical properties, wherein the results of the comparing for each of the circuit elements of interest that has only one electrical property in the one or more electrical properties are used to determine whether the each of the circuit elements of interest that has only one electrical property in the one or more electrical properties is active or not; and

determining whether each of the circuit elements of interest that has two or more electrical properties in the one or more electrical properties is active or not based on a logical combination of the results of the comparing for the each of the circuit elements of interest that has two or more electrical properties in the one or more electrical properties.

25. The system recited in claim 21 , wherein the one or more electrical properties are selected further based on information of potential defects associated with the each of circuit elements of interest.

26. The system recited in claim 25 , wherein the information of potential defects associated with the each of circuit elements of interest is determined based at least in part on layout information, properties of the each of circuit elements of interest, or any combination thereof.

27. The system recited in claim 21 , wherein the information of the each of circuit elements of interest further comprises whether the each of circuit elements of interest is a design-intent circuit element or a parasitic circuit element, whether the each of circuit elements of interest is a basic circuit element or a complex circuit element, signal frequencies applied to the each of circuit elements of interest, or any combination thereof.

28. The system recited in claim 21 , wherein the circuit elements of interest comprise all of or a subset of design-intent circuit elements of the circuit design.

29. The system recited in claim 28 , wherein the subset of design-intent circuit elements of the circuit design is randomly selected.

30. The system recited in claim 21 , wherein the activity coverage information comprises information about what percentage of the circuit elements of interest are active.

Assignments (3)
MERGER AND CHANGE OF NAME Recorded Jun 24, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 056647/0440 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2019
From: SUNTER, STEPHEN
To: MENTOR GRAPHICS (CANADA) ULC
Reel/Frame 048189/0797 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2019
From: MENTOR GRAPHICS (CANADA) ULC
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 048190/0016 →