IP Library Granted Patent US 10,797,823
Granted Patent B2
US 10,797,823 · App. 16/326,935 · Granted Oct 6, 2020

Terminal apparatus, base station apparatus, communication method, and integrated circuit

Inventors: Tomoki Yoshimura (Sakai, JP); Shoichi Suzuki (Sakai, JP); Wataru Ouchi (Sakai, JP); Liqing Liu (Sakai, JP); Kimihiko Imamura (Sakai, JP)
Assignees: SHARP KABUSHIKI KAISHA; FG INNOVATION COMPANY LIMITED
H04L1/0047H03M13/09H04L1/0038H04L1/0071H04L27/26H04L27/2649H04W72/04H04W72/0406
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Quick Facts
Patent No.
US 10,797,823
App. No.
16/326,935
Granted
Oct 6, 2020
Kind
B2
Abstract

A terminal apparatus includes: a receiver configured to detect a DCI format in a search space; a coding unit configured to divide a transport block into one or multiple code blocks, based at least on the DCI format and code the one or multiple code blocks to generate coded bits; and a transmitter configured to transmit the coded bits on a PUSCH. Multiplexed bits are given based at least on concatenation of the coded bits generated by coding the one or multiple code blocks. The coding unit maps the multiplexed bits to a matrix in a first-axis prioritized manner and reads out the multiplexed bits mapped to the matrix in the first-axis prioritized manner or a second-axis prioritized manner. Whether to prioritize the first axis or the second axis in a case of reading out the multiplexed bits mapped to the matrix, is based at least on whether or not the search space is CSS.

Claims (25)

1. A terminal device comprising:

encoding circuitry configured to and/or programmed to

divide a first sequence that is a transport block with Cyclic Redundancy Check (CRC) into a plurality of code blocks, and

generate coded bits including first coded bits or second coded bits by applying an error correcting code to the plurality of the code blocks, and

transmission circuitry configured to and/or programmed to transmit a second sequence on a Physical Uplink Shared Channel (PUSCH) scheduled by a Physical Downlink Control Channel (PDCCH), wherein

in a case that the PDCCH is detected in a first search space, the second sequence is given by mapping the first coded bits to a first matrix in a first-axis prioritized manner, and reading out the first coded bits in a second-axis prioritized manner, the first matrix being defined by a first axis and a second-axis and

in a case that the PDCCH is detected in a second search space, the second sequence is given by mapping the second coded bits to a second matrix in a third-axis prioritized manner, and reading out the second coded bits in a third-axis prioritized manner, the second matrix being defined by a third-axis and a fourth-axis.

2. A base station device comprising:

reception circuitry configured to and/or programmed to receive a second sequence on a Physical Uplink Shared Channel (PUSCH) scheduled by a Physical Downlink Control Channel (PDCCH), wherein

a first sequence that is a transport block with Cyclic Redundancy Check (CRC) is divided into a plurality of code blocks,

coded bits including first coded bits or second coded bits are generated by applying an error correcting code to the plurality of the code blocks,

in a case that the PDCCH is detected in a first search space, the second sequence is given by mapping the first coded bits to a first matrix in a first-axis prioritized manner, and reading out the first coded bits in a second-axis prioritized manner, the first matrix being defined by first-axis and a second-axis, and

in a case that the PDCCH is detected in a second search space, the second sequence is given by mapping the second coded bits to a second matrix in a third-axis prioritized manner, and reading out the second coded bits in a third-axis prioritized manner, the second matrix being defined by a third-axis and a fourth-axis.

3. A method of a terminal device, comprising:

dividing a first sequence that is a transport block with Cyclic Redundancy Check (CRC) into a plurality of code blocks,

generating coded bits including first coded bits or second coded bits by applying an error correcting code to the plurality of the code blocks, and

transmitting a second sequence on a Physical Uplink Shared Channel (PUSCH) scheduled by a Physical Downlink Control Channel (PDCCH), wherein

in a case that the PDCCH is detected in a first search space, the second sequence is given by mapping the first coded bits to a first matrix in a first-axis prioritized manner, and reading out the first coded bits in a second-axis prioritized manner, the first matrix being defined by a first-axis and a second-axis, and

in a case that the PDCCH is detected in a second search space, the second sequence is given by mapping the second coded bits to a second matrix in a third-axis prioritized manner, and reading out the second coded bits in a third-axis prioritized manner, the second matrix being defined by a third-axis and a fourth-axis.

4. A method of a base station device, comprising:

receiving a second sequence on a Physical Uplink Shared Channel (PUSCH) scheduled by a Physical Downlink Control Channel (PDCCH), wherein

a first sequence that is a transport block with Cyclic Redundancy Check (CRC) is divided into a plurality of code blocks,

coded bits including first coded bits or second coded bits are generated by applying an error correcting code to the plurality of the code blocks,

in a case that the PDCCH is detected in a first search space, the second sequence is given by mapping the first coded bits to a first matrix in a first-axis prioritized manner, and reading out the first coded bits in a second-axis prioritized manner, the first matrix being defined by a first-axis and a second-axis and

in a case that the PDCCH is detected in a second search space, the second sequence is given by mapping the second coded bits to a second matrix in a third-axis prioritized manner, and reading out the second coded bits in a third-axis prioritized manner, the second matrix being defined by a third-axis and a fourth-axis.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2023
From: SHARP KABUSHIKI KAISHA; SHARP CORPORATION
To: SHARP KABUSHIKI KAISHA
Reel/Frame 063815/0589 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2023
From: SHARP KABUSHIKI KAISHA; FG INNOVATION COMPANY LIMITED
To: SHARP KABUSHIKI KAISHA; SHARP CORPORATION
Reel/Frame 062389/0715 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2019
From: YOSHIMURA, TOMOKI; SUZUKI, SHOICHI; OUCHI, WATARU; LIU, LIQING; IMAMURA, KIMIHIKO
To: SHARP KABUSHIKI KAISHA; FG INNOVATION COMPANY LIMITED
Reel/Frame 049326/0607 →
Priority Claims (1)
JP 2016-171589 · Sep 2, 2016 · national
Continuity (1)
Related Publication 20190229847A1 · Jul 25, 2019
Cited By (1)
US 12,426,054