Thin film transistor having vertical channel and manufacturing method therefor, array substrate, display panel and display device
Disclosed are a thin film transistor and a manufacturing method therefor, an array substrate, a display panel and a display device. The thin film transistor includes a base substrate; a first electrode on the base substrate; a second electrode on the first electrode; an active layer provided on the base substrate and connecting the first electrode with the second electrode; and a gate electrode on the base substrate. The base substrate includes an upper surface facing towards the first electrode, the active layer includes a first side surface extending in a direction intersecting the upper surface of the base substrate, the first side surface connects the first electrode with the second electrode, and the gate electrode surrounds the first side surface.
1. A thin film transistor comprising:
a base substrate;
a first electrode on the base substrate;
a second electrode on the first electrode;
an active layer provided on the base substrate and connecting the first electrode with the second electrode; and
a gate electrode on the base substrate,
wherein the base substrate comprises an upper surface facing towards the first electrode, the active layer comprises a first side wall, a second side wall, a third side wall and a fourth side wall, each of the first side wall, the second side wall, the third side wall and the fourth side wall extending in a direction intersecting the upper surface of the base substrate;
wherein all of the first side wall, the second side wall, the third side wall and the fourth side wall connect the first electrode with the second electrode, and the gate electrode surrounds the first side wall, the second side wall, the third side wall and the fourth side wall;
wherein the active layer comprises a first contact face for contacting the first electrode, and a second contact face for contacting the second electrode;
wherein an area of a cross section of at least one of the first contact face or the second contact face in a direction parallel to the upper surface of the base substrate is larger than an area of a cross section of the first side wall in the direction parallel to the upper surface of the base substrate;
wherein an orthographic projection of each of the first side wall and the second side wall on the upper surface of the base substrate extends in a first direction, an orthographic projection of each of the third side wall and the fourth side wall on the upper surface of the base substrate extends in a second direction, both the first direction and the second direction are parallel to the upper surface of the base substrate, and the first direction is perpendicular to the second direction; and
wherein a length of the orthographic projection of the first side wall on the upper surface of the base substrate in the first direction is labeled as W 1 , a length of the orthographic projection of the second side wall on the upper surface of the base substrate in the first direction is labeled as W 2 , a length of the orthographic projection of the third side wall on the upper surface of the base substrate in the second direction is labeled as W 3 , and a length of the orthographic projection of the fourth side wall on the upper surface of the base substrate in the second direction is labeled as W 4 , and wherein W 1 is equal to W 2 , and W 3 is larger than W 4 .
2. The thin film transistor of claim 1 , wherein the thin film transistor further comprises a first insulating layer between the first electrode and the second electrode, the first insulating layer comprising at least four side surfaces, the at least four side surfaces of the first insulating layer being surfaces of the first insulating layer which are not in contact with the first electrode or the second electrode, and the active layer surrounding the at least four side surfaces of the first insulating layer.
3. The thin film transistor of claim 1 , wherein the active layer is positioned between the first electrode and the second electrode.
4. The thin film transistor of claim 3 , wherein an orthographic projection of the active layer on the base substrate is within an orthographic projection of each of the first electrode and the second electrode on the base substrate.
5. The thin film transistor of claim 1 , wherein the thin film transistor further comprises a second insulating layer between the active layer and the gate electrode.
6. The thin film transistor of claim 2 , wherein an orthographic projection of the active layer on the base substrate at least partially overlaps with an orthographic projection of the second electrode on the base substrate.
7. The thin film transistor of claim 1 , wherein an orthographic projection of the gate electrode on the base substrate covers an orthographic projection of the active layer on the base substrate.
8. The thin film transistor of claim 2 , wherein a material of at least one of the first insulating layer and the second insulating layer comprises aluminum oxide.
9. The thin film transistor of claim 1 , wherein at least one of the first electrode and the second electrode comprises a single-layer metal structure or a multilayer metal structure.
10. The thin film transistor of claim 2 , wherein a part of a cross section of each of the first insulating layer and the second electrode in a direction perpendicular the upper surface of to the base substrate has a positive trapezoidal shape.
11. An array substrate comprising the thin film transistor of claim 1 .
12. A display panel comprising the array substrate of claim 11 .
13. A display device comprising the display panel of claim 12 .
14. The thin film transistor of claim 1 , wherein an orthographic projection of the active layer on the base substrate covers an orthographic projection of the second electrode on the base substrate.