Apparatus, system and method of generating a frequency output with a digitally controlled ring oscillator (DCRO)
For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.
1. A digital Phase Locked Loop (PLL) comprising:
a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising:
a plurality of stages in a cyclic order, a stage of the plurality of stages comprising:
a plurality of inverter groups controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of other stages in the plurality of stages, wherein an inverter group of the plurality of inverter groups of the stage comprises a plurality of inverters connected in parallel;
a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and
a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.
2. The digital PLL of claim 1 , wherein the plurality of inverter groups of the stage are driven by an input to the stage, the input to the stage is based on outputs of two or more stages of the plurality of stages of the DCRO.
3. The digital PLL of claim 2 , wherein the input to the stage comprises a weighted combination of the outputs of the two or more stages of the plurality of stages.
4. The digital PLL of claim 1 , wherein the plurality of other stages comprises a first subsequent stage immediately subsequent to the stage according to the cyclic order, and a second subsequent stage separated from the stage by a predefined number of stages based on the cyclic order.
5. The digital PLL of claim 4 , wherein the predefined number of stages comprises an even number of stages.
6. The digital PLL of claim 4 , wherein the plurality of inverter groups of the stage comprises a first inverter group having an output to drive an input of the first subsequent stage; and a second inverter group having an output to drive an input of the second subsequent stage.
7. The digital PLL of claim 1 , wherein a weight of a first inverter group relative to a second inverter group of the plurality of inverter groups of the stage is based on a count of activated inverters in the first inverter group.
8. The digital PLL of claim 7 , wherein the frequency output is based on the weight of the first inverter group.
9. The digital PLL of claim 1 , wherein the decoder is configured to decode the phase of the DCRO based on a count of the plurality of stages of the DCRO.
10. The digital PLL of claim 1 , wherein a period of the DCRO is based on a count of the plurality of stages of the DCRO.
11. The digital PLL of claim 1 , wherein the phase error estimator comprises:
a frequency estimator to generate a phase frequency corresponding to a change in the phase of the DCRO by applying a delay operator to the phase of the DCRO;
a subtractor to generate a frequency error by subtracting the phase frequency from the frequency control word; and
an accumulator to generate the phase error based on the frequency error.
12. The digital PLL of claim 1 , wherein the plurality of stages of the DCRO comprises an odd number of stages.
13. The digital PLL of claim 1 , wherein the plurality of stages of the DCRO comprises more than three stages.
14. The digital PLL of claim 1 , wherein the plurality of stages of the DCRO comprises more than five stages.
15. The digital PLL of claim 1 , wherein the plurality of stages of the DCRO comprises more than ten stages.
16. The digital PLL of claim 1 comprising a fractional-N digital PLL to generate the frequency output as a non-integer multiple of a reference frequency, the sampled phases to be sampled according to the reference frequency.
17. A wireless communication device comprising:
one or more antennas;
a digital Phase Locked Loop (PLL) comprising:
a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising:
a plurality of stages in a cyclic order, a stage of the plurality of stages comprising:
a plurality of inverter groups controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of other stages in the plurality of stages, wherein an inverter group of the plurality of inverter groups of the stage comprises a plurality of inverters connected in parallel;
a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and
a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error; and
a radio to communicate over one or more wireless communication frequency channels based at least on the frequency output.
18. The wireless communication device of claim 17 , wherein the plurality of inverter groups of the stage are driven by an input to the stage, the input to the stage is based on outputs of two or more stages of the plurality of stages of the DCRO.
19. The wireless communication device of claim 18 , wherein the input to the stage comprises a weighted combination of the outputs of the two or more stages of the plurality of stages.
20. The wireless communication device of claim 17 , wherein the plurality of other stages comprises a first subsequent stage immediately subsequent to the stage according to the cyclic order, and a second subsequent stage separated from the stage by a predefined number of stages based on the cyclic order.
21. The wireless communication device of claim 17 , wherein a weight of a first inverter group relative to a second inverter group of the plurality of inverter groups of the stage is based on a count of activated inverters in the first inverter group.
22. The wireless communication device of claim 17 , wherein the decoder is configured to decode the phase of the DCRO based on a count of the plurality of stages of the DCRO.
23. A product comprising one or more tangible computer-readable non-transitory storage media comprising computer-executable instructions operable to, when executed by at least one computer processor, enable the at least one computer processor to cause a digital Phase Locked Loop (PLL) to:
generate a frequency output of a digitally controlled Ring Oscillator (DCRO) based on a control signal, the DCRO comprising:
a plurality of stages in a cyclic order, a stage of the plurality of stages comprising:
a plurality of inverter groups controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of other stages in the plurality of stages, wherein an inverter group of the plurality of inverter groups of the stage comprises a plurality of inverters connected in parallel;
decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO;
estimate a phase error based on the phase of the DCRO and a frequency control word; and
generate the control signal based on the phase error.
24. The product of claim 23 , wherein the plurality of inverter groups of the stage are driven by an input to the stage, the input to the stage is based on outputs of two or more stages of the plurality of stages of the DCRO.
25. The product of claim 23 , wherein the plurality of other stages comprises a first subsequent stage immediately subsequent to the stage according to the cyclic order, and a second subsequent stage separated from the stage by a predefined number of stages based on the cyclic order.