Array substrate, display apparatus, and method of fabricating array substrate

1. An array substrate, comprising:

a base substrate;

a first thin film transistor on the base substrate and comprising a first active layer, a first gate electrode, a first source electrode and a first drain electrode, the first active layer being a silicon active layer;

a second thin film transistor on the base substrate and comprising a second active layer, a second gate electrode, a second source electrode and a second drain electrode, the second active layer being a metal oxide active layer;

a first gate insulating layer between the first active layer and the first gate electrode;

a second gate insulating layer between the second active layer and the second gate electrode, the second gate insulating layer being different from the first gate insulating layer;

an insulating layer on a side of the first gate electrode distal to the base substrate;

a capacitor electrode on a side of the insulating layer distal to the first gate electrode; and

a buffer layer on a side of the capacitor electrode distal to the base substrate;

wherein the first source electrode, the first drain electrode, and the second gate electrode are in a same layer;

the first source electrode and the first drain electrode are on a side of the second gate insulating layer distal to the base substrate;

the capacitor electrode and the first gate electrode constitute a storage capacitor in the first thin film transistor;

the buffer layer is in direct contact with the second active layer; and

at least a sub-layer of the buffer layer that is in direct contact with the second active layer comprises SiO x , 0<x<2.

2. The array substrate of claim 1 , wherein the second gate insulating layer is in direct contact with the first source electrode and the first drain electrode.

3. The array substrate of claim 1 , wherein the insulating layer is in direct contact with the capacitor electrode and the first gate electrode; and

the insulating layer has a thickness in a range of approximately 100 nm to approximately 250 nm.

4. The array substrate of claim 1 , further comprising a first inter-layer dielectric layer on a side of the capacitor electrode distal to the base substrate; and

a buffer layer on a side of the first inter-layer dielectric layer distal to the base substrate.

5. The array substrate of claim 1 , wherein the sub-layer of the buffer layer comprising SiO x and in direct contact with the second active layer has a thickness greater than approximately 200 nm.

6. An array substrate, comprising:

a base substrate;

a first thin film transistor on the base substrate and comprising a first active layer, a first gate electrode, a first source electrode and a first drain electrode, the first active layer being a silicon active layer;

a second thin film transistor on the base substrate and comprising a second active layer, a second gate electrode, a second source electrode and a second drain electrode, the second active layer being a metal oxide active layer;

a first gate insulating layer between the first active layer and the first gate electrode:

a second gate insulating layer between the second active layer and the second gate electrode, the second gate insulating layer being different from the first gate insulating layer;

an insulating layer on a side of the first gate electrode distal to the base substrate;

a first inter-layer dielectric layer on a side of the insulating layer distal to the base substrate;

a buffer layer on a side of the first inter-layer dielectric layer distal to the base substrate; and

a first via and a second via respectively extending through the second gate insulating layer, the buffer layer, the first inter-layer dielectric layer, and the insulating layer;

wherein the first source electrode, the first drain electrode, and the second gate electrode are in a same layer;

the first source electrode and the first drain electrode are on a side of the second gate insulating layer distal to the base substrate;

the first source electrode is electrically connected to the first active layer through the first via; and

the first drain electrode is electrically connected to the first active layer through the second via.

7. An array substrate, comprising:

a base substrate;

a first thin film transistor on the base substrate and comprising a first active layer, a first gate electrode, a first source electrode and a first drain electrode, the first active layer being a silicon active layer;

a second thin film transistor on the base substrate and comprising a second active layer, a second gate electrode, a second source electrode and a second drain electrode, the second active layer being a metal oxide active layer;

a first gate insulating layer between the first active layer and the first gate electrode:

a second gate insulating layer between the second active layer and the second gate electrode, the second gate insulating layer being different from the first gate insulating layer; and

a second inter-layer dielectric layer on a side of the second gate electrode, the second active layer, the first source electrode, and the first drain electrode distal to the base substrate;

wherein the first source electrode, the first drain electrode, and the second gate electrode are in a same layer;

the first source electrode and the first drain electrode are on a side of the second gate insulating layer distal to the base substrate;

the second inter-layer dielectric layer is in direct contact with a source electrode contact part and a drain electrode contact part of the second active layer; and

at least a sub-layer of the second inter-layer dielectric layer that is in direct contact with the source electrode contact part and the drain electrode contact part of the second active layer comprises SiO x , 0<x<2.

8. The array substrate of claim 7 , wherein the sub-layer of the second inter-layer dielectric layer comprising SiO x and in direct contact with the source electrode contact part and the drain electrode contact part of the second active layer has a thickness greater than approximately 200 nm.

9. The array substrate of claim 7 , further comprising a passivation layer on a side of the second inter-layer dielectric layer distal to the base substrate; and

a third via and a fourth via respectively extending through the passivation layer and the second inter-layer dielectric layer;

wherein the second source electrode is electrically connected to the second active layer through the third via; and

the second drain electrode is electrically connected to the second active layer through the fourth via.

10. The array substrate of claim 9 , further comprising:

a relay electrode electrically connected to the first drain electrode; and

a fifth via extending through the passivation layer and the second inter-layer dielectric layer;

wherein the relay electrode, the second source electrode, and the second drain electrode are in a same layer, and on a side of the passivation layer distal to the base substrate; and

the relay electrode is electrically connected to the first drain electrode through the fifth via.

11. The array substrate of claim 10 , wherein the array substrate has a display area and a peripheral area; and

the first thin film transistor and the second thin film transistor are in the display area;

wherein the array substrate in the peripheral area further comprises:

a signal line layer;

a sixth via extending through at least one layer of the array substrate; and

an organic filler layer filling the sixth via for enhancing flexibility in the peripheral area;

wherein the signal line layer is in a same layer as the relay electrode, the second source electrode, and the second drain electrode; and

the signal line layer is on a side of the organic filler layer distal to the base substrate.

12. The array substrate of claim 1 , further comprising a light shielding layer configured to shield light from irradiating on the second active layer;

wherein the light shielding layer is in a same layer as one of the capacitor electrode and the first gate electrode.

13. The array substrate of claim 12 , wherein the light shielding layer and the second gate electrode constitute a double-gate structure of the second thin film transistor.

14. The array substrate of claim 2 , wherein the second gate insulating layer comprises SiO x , 0<x<2.

15. A display apparatus, comprising the array substrate of claim 1 .

16. A display apparatus, comprising the array substrate of claim 6 .

17. A display apparatus, comprising the array substrate of claim 7 .