Camera device
The present invention provides a camera device capable of quickly processing image data while suppressing bus traffic. In the present invention, an image memory 50 is connected to a memory bus 70 and stores a right source image 220 and a left source image 210 . A memory access management 40 is connected to the memory bus 70 and to an internal bus 80 , reads the right source image 220 and the left source image 210 from the image memory 50 via the memory bus 70 , and outputs the read right source image 220 and the left source image 210 to the internal bus 80 . Processing unit A 30 , processing unit B 31 , and processing unit C 32 are connected to the internal bus 80 and process the image data output to the internal bus 80.
1. A camera device comprising:
at least one camera configured to photograph an image and generate image data of the image;
a first bus coupled to the at least one camera;
a first memory coupled to the first bus to store the image data;
a second bus;
a second memory;
a memory access management controller coupled to the first bus and including a data buffer coupled to the second bus; and
a plurality of processors coupled to the second bus and configured to receive and process the image data output to the second bus from the data buffer,
wherein each respective processor of the plurality of processors is configured to detect an execution state of the respective processor and transmit the execution state via control signal to the memory access management controller, the plurality of processors comprising:
at least a first processor configured to receive the image data from a first line to a second line,
at least a second processor configured to receive the image data from a third line, located between the first line and the second line, to a fourth line; and
wherein the memory access management controller is configured to:
read the image data from the first memory via the first bus and output the read image data to the data buffer,
responsive to determining that the first processor receives the image data based on the execution state received via control signal, store the image data from the third line to the second line in the second memory and stop reading of the image data after a line next to the second line, and
responsive to determining that the second processor receives the image data based on the execution state received via control signal, output the image data from the third line to the second line stored in the second memory to the second bus.
2. The camera device according to claim 1 , wherein the memory access management controller is configured to read the image data line by line, and to output the read image data to the second bus via the data buffer line by line.
3. The camera device according to claim 2 , wherein
the first processor is configured to correct distortion of the image data from the first line to the second line, and
the second processor is configured to correct distortion of the image data from the third line to the fourth line.
4. The camera device according to claim 1 , wherein an amount of data read from the first memory by the memory access controller is smaller than a total sum of an amount of data processed by each of the plurality of processors.
5. The camera device according to claim 1 , wherein each of the plurality of processors is configured to process the image data of different regions,
the respective regions have a portion overlapped with other regions, and
the memory access controller is configured to read the image data of the region according to priority corresponding to the region, and output the read image data of the region to the second bus.
6. A camera device comprising:
at least one camera configured to photograph an image and generate image data of the image;
a first bus coupled to the at least one camera;
a first memory coupled to the first bus to store the image data;
a second bus;
a second memory;
a memory access management controller coupled to the first bus and including a data buffer coupled to the second bus; and
a plurality of processors coupled to the second bus and configured to receive and process the image data output to the second bus from the data buffer, the plurality of processors comprising:
at least a first processor configured to receive the image data from a first line to a second line, and correct distortion of the received image data, and
at least a second processor configured to receive the image data from a third line, located between the first line and the second line, to a fourth line, and correct distortion of the received image data;
wherein the memory access management controller is configured to:
read the image data from the first memory line by line via the first bus and to output the read image data to the second bus via the data buffer line by line,
store the image data from the third line to the second line in the second memory and stop reading of the image data after a line next to the second line responsive to determining that the first processor receives the image data and the second processor does not receive the image data, and
output the image data from the third line to the second line stored in the second memory to the second bus responsive to determining that the second processor receives the image data.