Driving method for display panel, driving circuit, display panel and display device

1. A pixel circuit for a display panel, wherein the display panel is configured to display multiple frames of image to be displayed, the image to be displayed comprises a plurality of image pixel units, the display panel comprises a plurality of display pixel units, each of the display pixel units is provided with the pixel circuit,

the pixel circuit comprises a display voltage writing sub-circuit, a storage sub-circuit, a driving transistor and a light-emitting element,

an input terminal of the display voltage writing sub-circuit is coupled to a data line, an output terminal of the display voltage writing sub-circuit is coupled to an input terminal of the storage sub-circuit, and a control terminal of the display voltage writing sub-circuit is coupled to a first scanning signal line;

a first output terminal of the storage sub-circuit is coupled to a gate of the driving transistor, a second output terminal of the storage sub-circuit is coupled to a second electrode of the driving transistor, and a control terminal of the storage sub-circuit is coupled to a second scanning signal line;

the first electrode of the driving transistor is coupled to a high level signal terminal, wherein

a third output terminal of the storage sub-circuit is coupled to an anode of the light-emitting element,

the pixel circuit further comprises a duty-ratio control sub-circuit, and a control terminal of the duty-ratio control sub-circuit is coupled to a third scanning signal line, an input terminal of the duty-ratio control sub-circuit is coupled to the second electrode of the driving transistor, and an output terminal of the duty-ratio control sub-circuit is coupled to the anode of the light-emitting element, and in a case where a first level signal is received by the control terminal of the duty-ratio control sub-circuit, the input terminal of the duty-ratio control sub-circuit is electrically coupled to the output terminal of the duty-ratio control sub-circuit, wherein during a duration of one frame of image, a duration of the first level signal is positively correlated with a grayscale value of an image pixel unit corresponding to the pixel circuit, a voltage of the first level signal is lower than a voltage provided when the display pixel unit is driven according to a predetermined value, wherein

the storage sub-circuit comprises a storage capacitor, a first storage control transistor, and a second storage control transistor,

one end of the storage capacitor is coupled to the output terminal of the display voltage writing sub-circuit, and another end of the storage capacitor is configured as the first output terminal of the storage sub-circuit;

a gate of the first storage control transistor is coupled to a gate of the second storage control transistor, and is configured as the control terminal of the storage sub-circuit, a first electrode of the first storage control transistor is coupled to the one end of the storage capacitor, a second electrode of the second storage control transistor is configured as the third output terminal of the storage sub-circuit;

a first electrode of the second storage control transistor is coupled to the another end of the storage capacitor, and a second electrode of the second storage control transistor is configured as the second output terminal of the storage sub-circuit.

2. The pixel circuit according to claim 1 , wherein the duty-ratio control sub-circuit comprises a duty-ratio control transistor, a gate of the duty-ratio control transistor is configured as the control terminal of the duty-ratio control sub-circuit, a first electrode of the duty-ratio control transistor is configured as the input terminal of the duty-ratio control sub-circuit, and a second electrode of the duty-ratio control transistor is configured as the output terminal of the duty-ratio control sub-circuit.

3. The pixel circuit according to claim 2 , wherein in a case where a second level signal is received by the gate of the duty-ratio control transistor, the first electrode of the duty-ratio control transistor is disconnected from the second electrode of the duty-ratio control transistor.

4. The pixel circuit according to claim 1 , wherein the display voltage writing sub-circuit comprises a data writing transistor, a gate of the data writing transistor is configured as the control terminal of the display voltage writing sub-circuit, a first electrode of the data writing transistor is configured as the input terminal of the display voltage writing sub-circuit, and a second electrode of the data voltage writing transistor is configured as the output terminal of the display voltage writing sub-circuit.

5. A display panel comprising a plurality of display pixel units arranged in multiple rows and multiple columns, each of the display pixel units being provided with a pixel circuit of claim 1 , wherein the display panel comprises a plurality of first scanning lines, a plurality of second scanning lines, and a plurality of third scanning lines, and each row of display pixel units correspond to one of the first scanning lines, each row of display pixel units correspond to one of the second scanning lines, and each row of display pixel units correspond to one of the third scanning lines,

control terminals of the display voltage writing sub-circuits of the pixel circuits in a same row are coupled to a corresponding one of the first scanning lines, control terminals of the storage sub-circuits of the pixel circuits in a same row are coupled to a corresponding one of the second scanning lines, and control terminals of the duty-ratio control sub-circuits of the pixel circuits in a same row are coupled to a corresponding one of the third scanning lines.

6. A display panel comprising a plurality of display pixel units arranged in multiple rows and multiple columns, each of the display pixel units being provided with a pixel circuit of claim 2 , wherein the display panel comprises a plurality of first scanning lines, a plurality of second scanning lines, and a plurality of third scanning lines, and each row of display pixel units correspond to one of the first scanning lines, each row of display pixel units correspond to one of the second scanning lines, and each row of display pixel units correspond to one of the third scanning lines,

control terminals of the display voltage writing sub-circuits of the pixel circuits in a same row are coupled to a corresponding one of the first scanning lines, control terminals of the storage sub-circuits of the pixel circuits in a same row are coupled to a corresponding one of the second scanning lines, and control terminals of the duty-ratio control sub-circuits of the pixel circuits in a same row are coupled to a corresponding one of the third scanning lines.

7. A display panel comprising a plurality of display pixel units arranged in multiple rows and multiple columns, each of the display pixel units being provided with a pixel circuit of claim 3 , wherein the display panel comprises a plurality of first scanning lines, a plurality of second scanning lines, and a plurality of third scanning lines, and each row of display pixel units correspond to one of the first scanning lines, each row of display pixel units correspond to one of the second scanning lines, and each row of display pixel units correspond to one of the third scanning lines,

control terminals of the display voltage writing sub-circuits of the pixel circuits in a same row are coupled to a corresponding one of the first scanning lines, control terminals of the storage sub-circuits of the pixel circuits in a same row are coupled to a corresponding one of the second scanning lines, and control terminals of the duty-ratio control sub-circuits of the pixel circuits in a same row are coupled to a corresponding one of the third scanning lines.

8. A display panel comprising a plurality of display pixel units arranged in multiple rows and multiple columns, each of the display pixel units being provided with a pixel circuit of claim 4 , wherein the display panel comprises a plurality of first scanning lines, a plurality of second scanning lines, and a plurality of third scanning lines, and each row of display pixel units correspond to one of the first scanning lines, each row of display pixel units correspond to one of the second scanning lines, and each row of display pixel units correspond to one of the third scanning lines,

control terminals of the display voltage writing sub-circuits of the pixel circuits in a same row are coupled to a corresponding one of the first scanning lines, control terminals of the storage sub-circuits of the pixel circuits in a same row are coupled to a corresponding one of the second scanning lines, and control terminals of the duty-ratio control sub-circuits of the pixel circuits in a same row are coupled to a corresponding one of the third scanning lines.

9. A display device comprising the display panel of claim 5 and a driving circuit, the driving circuit comprises a grayscale detecting sub-circuit, configured to detect a grayscale value of each of the image pixel units in the image to be displayed; a determining sub-circuit, configured to compare the grayscale value of each of the image pixel units with a predetermined value, and generate a first determination signal when the grayscale value of the image pixel unit is greater than the predetermined value; a display voltage providing sub-circuit, configured to provide a predetermined display voltage to a display pixel unit corresponding to the image pixel unit having the grayscale value greater than the predetermined value according to the first determination signal, and during one frame of image, a duration of the predetermined display voltage is positively correlated with the grayscale value, which is greater than the predetermined value, of the image pixel unit, the predetermined display voltage is lower than a voltage provided when the display pixel unit is driven according to the predetermined value, wherein

the display voltage writing sub-circuit of the driving circuit is electrically coupled to a data line.