IP Library Granted Patent US 11,139,434
Granted Patent B2
US 11,139,434 · App. 16/343,506 · Granted Oct 5, 2021

Improving stability of thin film transistors

Inventor: Guillaume Fichet (Cambridge, GB)
Assignee: FLEXENBLE LIMITED
H01L51/0025B01D53/261F26B5/045H01L27/283H01L51/0026H01L51/0031H01L51/0541B01D2253/116H01L51/0512
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,139,434
App. No.
16/343,506
Granted
Oct 5, 2021
Kind
B2
Abstract

A technique comprising: producing an unencapsulated stack of layers defining one or more electronic devices including an organic semiconductor element; and then subjecting the unencapsulated stack of layers to a water removal treatment in a vacuum oven in the presence of an external water adsorbent; wherein the water removal treatment comprises heating the unencapsulated stack of layers in the vacuum oven for a time period longer than a control time period at which a spike in oven pressure attributable to the release of water from the stack of layers would occur with heating under the same treatment conditions but without the water absorbing material.

Claims (13)

1. A method comprising: producing an unencapsulated stack of layers defining one or more electronic devices including an organic semiconductor element; and then subjecting the unencapsulated stack of layers to a water removal treatment in a vacuum oven in the presence of an external water adsorbent; wherein the water removal treatment comprises heating the unencapsulated stack of layers in the vacuum oven for a time period longer than a control time period at which a spike in oven pressure attributable to the release of water from the stack of layers would occur with heating under the same treatment conditions but without the water absorbing material.

2. The method according to claim 1 comprising heating the stack of layers in the vacuum oven for a time period at least 20 times as long as the control time period, and preferably at least as 30 times as long as the control time period.

3. The method according to claim 1 , wherein the water removal treatment comprises heating the stack of layers in the vacuum oven whilst packed in the external water adsorbent.

4. The method according to claim 1 , wherein the external water adsorbent has a water capacity at 25° C. (grams of water adsorbable per 100 grams of water adsorbent) and a relative humidity of 10% of 15 g or more.

5. The method according to claim 1 , wherein the water absorbent is a molecular sieve material.

6. A method comprising: producing an unencapsulated stack of layers defining one or more transistor devices including an organic semiconductor channel; and then subjecting the unencapsulated stack of layers to a water removal treatment in a vacuum oven; wherein the water removal treatment comprises heating the unencapsulated stack of layers in the vacuum oven in the presence of a water adsorbent for a time sufficient to remove water to an extent that the one or more transistor devices exhibit, after encapsulation of the stack, a variation in gate voltage of less than 6% in a stress test in air involving maintaining the gate voltage at a level required to achieve a current of 2.5 μA through the organic semiconductor channel for 60 hours.

7. A method comprising: producing an unencapsulated stack of layers defining one or more transistor devices including an organic semiconductor channel; and then subjecting the unencapsulated stack of layers to a water removal treatment in a vacuum oven; wherein the water removal treatment comprises heating the unencapsulated stack of layers in the vacuum oven in the presence of a water adsorbent for a time sufficient to remove water to an extent that the one or more transistor devices exhibit, after encapsulation of the stack, a variation in forward current through the organic semiconductor channel of less than about 5% in a stress test involving operating the one or more transistor devices at a fixed gate voltage and a fixed source-drain voltage for 90 hours in air at 60° C.

8. The method according to claim 6 , wherein the water removal treatment comprises heating the stack of layers in the vacuum oven whilst packed in the external water adsorbent.

9. The method according to claim 6 , wherein the external water adsorbent has a water capacity at 25° C. (grams of water adsorbable per 100 grams of water adsorbent) and a relative humidity of 10% of 15 g or more.

10. The method according to claim 6 , wherein the water absorbent material is a molecular sieve.

11. The method according to claim 7 , wherein the water removal treatment comprises heating the stack of layers in the vacuum oven whilst packed in the external water adsorbent.

12. The method according to claim 7 , wherein the external water adsorbent has a water capacity at 25° C. (grams of water adsorbable per 100 grams of water adsorbent) and a relative humidity of 10% of 15 g or more.

13. The method according to claim 7 , wherein the water absorbent material is a molecular sieve.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2023
From: FLEXENABLE LIMITED (IN ADMINISTRATION)
To: FLEXENABLE TECHNOLOGY LIMITED
Reel/Frame 062959/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2019
From: FICHET, GUILLAUME
To: FLEXENABLE LIMITED
Reel/Frame 049582/0827 →
Priority Claims (1)
GB 1617775 · Oct 20, 2016 · national
Continuity (1)
Related Publication 20190267549A1 · Aug 29, 2019