Reception apparatus, communication system, and clock recovery method
According to one embodiment, there is provided a reception apparatus including a preamplifier and a clock recovery circuit. The preamplifier is configured to receive data through a wired transmission path. The clock recovery circuit is configured to sample a value during an edge period and a value during a data period, which are in data received from the preamplifier, by using a reference clock, to execute a phase adjustment to the reference clock with respect to a transition timing of a signal level of the data in a case sampling results is satisfied a particular condition concerning a transition of the signal level of the data, and to execute no phase adjustment to the reference clock with respect to the transition timing of the signal level of the data in a case the sampling results is not satisfied the particular condition.
1. A reception apparatus comprising:
a preamplifier configured to receive a first data through a wired transmission path; and
a clock recovery circuit configured to sample a lue during an edge period and a value during a data period, which are in a second data received from the preamplifier, by utilizing a reference clock, to execute a phase adjustment to the reference clock with respect to a transition timing of a signal level of the received second data in a case where a pattern of sampling results matches a specific pattern, the specific pattern including a pattern of at least three bits of data sampling results and one bit of an edge sampling result between the three bits of the data sampling results, sampling timing interval between one of timings to the data sampling results and a timing to the edge sampling result being smaller than sampling timing interval between adjacent two timings among the timings to the data sampling results, and to execute no phase adjustment to the reference clock with respect to the transition timing of the signal level of the received second data in a case where the pattern of the sampling results does not match the specific pattern.
2. The reception apparatus according to claim 1 , wherein
the specific pattern includes at least one of a pattern corresponding to that a compensation amount in the preamplifier is excessive, a pattern corresponding to that an output of the preamplifier contains an offset voltage, and a pattern corresponding to that an output of the preamplifier contains a Duty Cycle Distortion (DCD).
3. The reception apparatus according to claim 1 , wherein
the specific pattern includes an (n−2)-th data sampling result, an (n−1)-th data sampling result, an n-th edge sampling result, and an n-th data sampling result, where “n” is an integer of 2 or more.
4. The reception apparatus according to claim 1 , wherein
the specific pattern includes an (n−1)-th data sampling result, an n-th edge sampling result, an n-th data sampling result, and an (n+1)-th data sampling result, where “n” is an integer of 1 or more.
5. The reception apparatus according to claim 1 , wherein
the specific pattern includes a pattern of four bits of sampling results and one bit of an edge sampling result among the four bits of the data sampling results.
6. The reception apparatus according to claim 5 , wherein
the specific pattern includes an (n−2)-th data sampling result, an (n−1)-th data sampling result, an n-th edge sampling result, an n-th data sampling result, and an (n+1)-th data sampling result, where “n” is an integer of 2 or more.
7. The reception apparatus according to claim 1 , wherein
the specific pattern includes a pattern of the sampling results corresponding to one of a rising edge portion and a falling edge portion in a waveform of the received second data.
8. The reception apparatus according to claim 1 , wherein
the specific pattern includes a pattern of the sampling results corresponding to one of an even-numbered edge portion and an odd-numbered edge portion in a waveform of the received second data.
9. The reception apparatus according to claim 1 , wherein
the specific pattern includes a pattern of the sampling results corresponding to a data pattern of three bits in which 0 and 1 are mixed, and a pattern of the sampling results corresponding to one of a rising edge portion and a falling edge portion in a waveform.
10. The reception apparatus according to claim 1 , wherein
the specific pattern includes a pattern of the sampling results corresponding to a data pattern of three bits in which 0 and 1 are mixed, and a pattern of the sampling results corresponding to one of an even-numbered edge portion and an odd-numbered edge portion in a waveform.
11. A communication system comprising:
a transmission apparatus; and
the reception apparatus according to claim 1 , to which the transmission apparatus is connected through a wired communication path.
12. The communication system according to claim 11 , wherein
the specific pattern includes at least one of a pattern corresponding to that a compensation amount in the preamplifier is excessive, a pattern corresponding to that an output of the preamplifier contains an offset voltage, and a pattern corresponding to that an output of the preamplifier contains a Duty Cycle Distortion (DCD).
13. The communication system according to claim 11 , wherein
the specific pattern includes at least one of a pattern of four bits of the data sampling results and one bit of an edge sampling result between the four bits of the data sampling results, a pattern of the sampling results corresponding to one of a rising edge portion and a falling edge portion in a waveform of the received second data, and a pattern of the sampling results corresponding to one of an even-numbered edge portion and an odd-numbered edge portion in a waveform of the received second data.
14. The reception apparatus according to claim 1 , wherein
the clock recovery circuit has a first mode and a second mode,
the clock recovery circuit is configured:
in the first mode and the second mode, to sample the value during the edge period and the value during the data period, which are in the second data received from the preamplifier, by utilizing the reference clock,
in the first mode, to execute the phase adjustment to the reference clock with respect to the transition timing of the signal level of the received second data in a case where the pattern of the sampling results matches the specific pattern and to execute no phase adjustment to the reference clock with respect to the transition timing of the signal level of the received second data in a case where the pattern of the sampling results does not match the specific pattern,
in the second mode, to execute the phase adjustment to the reference clock with respect to the transition timing of the signal level of the received second data for every sampling results.
15. A clock recovery method comprising:
receiving data;
sampling a value during an edge period and a value during a data period, which are in the received data, by utilizing a reference clock;
executing a phase adjustment to the reference clock with respect to a transition timing of a signal level of the received data in a case where a pattern of sampling results matches a specific pattern, the specific pattern including a pattern of at least three bits of data sampling results and one bit of an edge sampling result between the three bits of the data sampling results, sampling timing interval between one of timings to the data sampling results and a timing to the edge sampling result being smaller than sampling timing interval between adjacent two timing among the timings to the data sampling results; and
executing no phase adjustment to the reference clock with respect to the transition timing of the signal level of the received data in the case where a pattern of the sampling results does not match the specific pattern.
16. The dock recovery method according to claim 15 , wherein
the specific pattern includes at least one of a pattern corresponding to that a compensation amount in the preamplifier is excessive, a pattern corresponding to that an output of the preamplifier contains an offset voltage, and a pattern corresponding to that an output of the preamplifier contains a Duty Cycle Distortion (DCD).
17. The clock recovery method according to claim 15 , wherein
the specific pattern includes at least one of a pattern of four bits of the data sampling results and one bit of an edge sampling result between the four bits of the data sampling results, a pattern of the sampling results corresponding to one of a rising edge portion and a falling edge portion in a waveform of the received data, and a pattern of the sampling results corresponding to one of an even-numbered edge portion and an odd-numbered edge portion in a waveform of the received data.
18. The clock recovery method according to claim 15 , wherein
the sampling includes in a first mode and a second mode of clock recovery, sampling the value during the edge period and the value during the data period, which are in the received data, by utilizing the reference clock,
the executing includes
in the first mode of clock recovery, executing a phase adjustment to the reference clock with respect to the transition timing of the signal level of the received data in a case where the pattern of the sampling results matches the specific pattern, and executing no phase adjustment to the reference clock with respect to the transition timing of the signal level of the received data in a case where the pattern of the sampling results does not match the specific pattern; and
in the second mode of clock recovery, executing the phase adjustment to the reference clock with respect to the transition timing of the signal level of the received data for every sampling results.