Memory system that carries out soft bit decoding
A memory system includes a nonvolatile semiconductor memory and a controller. The controller is configured to maintain a plurality of log likelihood ratio (LLR) tables for predicting a value of data read from the nonvolatile semiconductor memory, count a number of times that each of write operations, erase operations, and read operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on the counted number of the read operations and one of the counted number of the write operations and the counted number of the erase operations, which correspond to a target unit storage region of a read operation, and carry out decoding of data read from the target unit storage region of the read operation, using one of the LLR tables selected according to the determined order.
1. A memory system comprising:
a nonvolatile semiconductor memory; and
a controller configured to
maintain a plurality of log likelihood ratio (LLR) tables for correcting data read from the nonvolatile semiconductor memory,
count a number of times at least one of write operations, erase operations, and read operations having been carried out with respect to each unit storage region of the nonvolatile semiconductor memory,
determine an order in which the LLR tables are referred to, on the basis of the counted number corresponding to a target unit storage region of a read operation, and
carry out correcting of data read from the target unit storage region of the read operation, using one of the LLR tables selected according to the determined order.
2. The memory system according to claim 1 , wherein
the plurality of LLR tables includes
a first plurality of LLR tables that are each different depending on the number of times of the write operations and the number of times of the erase operations, and
a second plurality of LLR tables that are each different depending on the number of times of the read operations.
3. The memory system according to claim 1 , wherein
the unit storage region is a unit of erasing data from the nonvolatile semiconductor memory.
4. The memory system according to claim 3 , wherein
the unit of erasing data is a block of memory cells arranged in rows and columns.
5. The memory system according to claim 3 , wherein
the unit of erasing data is a page of memory cells arranged in a single row across multiple columns.
6. The memory system according to claim 1 , wherein
the controller carries out the correcting using a next LLR table in the determined order, when the correcting using the selected LLR table fails.
7. The memory system according to claim 1 , wherein
the data read from the target unit storage region include a plurality of values that are sensed using different read voltages.
8. The memory system according to claim 1 , wherein
the controller, prior to carrying out correcting of data read from the target unit storage region of the read operation using the selected LLR table, performs a hard bit reading using a preset read voltage and a hard bit decoding processing on data read using the hard bit reading.
9. The memory system according to claim 8 , wherein
the controller performs a soft bit reading using a plurality of read voltages after determining that the hard bit reading fails.
10. The memory system according to claim 9 , wherein
the data read using the soft bit reading are corrected by the controller using the selected LLR table.
11. The memory system according to claim 1 , wherein
the controller maintains a number of times of successful correction of data read by the read operation, using each LLR table.
12. The memory system according to claim 11 , wherein
the controller determines the order in which the LLR tables are referred to, further on the basis of the number of times of successful correction of data.