Enabling product SKUs based on chiplet configurations
A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.
1. A general-purpose graphics processor comprising:
a base die including an interconnect fabric; and
one or more chiplets coupled with the base die and the interconnect fabric via an interconnect structure, the interconnect structure to enable electrical communication between the one or more chiplets and the interconnect fabric, wherein the one or more chiplets are interchangeable during assembly of the general-purpose graphics processor, the one or more chiplets include a first logic chiplet coupled with the base die and connected to the interconnect fabric via a first interconnect structure, the first interconnect structure is bonded to a first logic chiplet slot, and the first logic chiplet includes functional units configured to perform general-purpose graphics processing operations; and
wherein the first logic chiplet slot is configurable to accept a logic chiplet selected from a group including the first logic chiplet and a third logic chiplet that includes functional units configured to perform matrix acceleration operations.
2. The general-purpose graphics processor as in claim 1 , wherein the one or more chiplets include a memory chiplet including memory cells associated with a memory device, the memory chiplet coupled to a first memory chiplet slot.
3. The general-purpose graphics processor as in claim 2 , wherein the one or more chiplets include a second logic chiplet.
4. The general-purpose graphics processor as in claim 3 , wherein the memory chiplet includes cache memory cells.
5. The general-purpose graphics processor as in claim 4 , wherein the second logic chiplet is coupled with the base die and connected to the interconnect fabric via a second interconnect structure, the second interconnect structure bonded to a second logic chiplet slot.
6. The general-purpose graphics processor as in claim 5 , wherein the interconnect structure is a silicon interconnect structure.
7. The general-purpose graphics processor as in claim 6 , wherein the second logic chiplet slot is configured to accept the second logic chiplet or a fourth logic chiplet, wherein the second logic chiplet includes functional units configured to perform media encode or decode operations and the fourth logic chiplet includes a network processor and a physical network interface.
8. The general-purpose graphics processor as in claim 7 , wherein each chiplet is independently power gated.
9. The general-purpose graphics processor as in claim 8 , wherein a logic chiplet includes a first layer including functional units and second layer including a fabric interconnect node.
10. The general-purpose graphics processor as in claim 9 , wherein a memory chiplet includes a first layer including a bank of memory cells and second layer including I/O circuits associated with an interconnect bridge between the memory chiplet and a logic chiplet.
11. The general-purpose graphics processor as in claim 1 , wherein the base die is a first base die and the first base die couples with a second base die via an interconnect bridge.
12. A data processing system comprising:
a general-purpose graphics processor comprising a base die including an interconnect fabric and one or more chiplets coupled with the base die and the interconnect fabric via an interconnect structure, the interconnect structure to enable electrical communication between the one or more chiplets and the interconnect fabric, wherein the one or more chiplets are interchangeable during assembly of the general-purpose graphics processor, the one or more chiplets include a first logic chiplet coupled with the base die and connected to the interconnect fabric via a first interconnect structure, the first interconnect structure bonded to a first logic chiplet slot, the first logic chiplet slot is configurable to accept a logic chiplet selected from a group including the first logic chiplet and a third logic chiplet, the first logic chiplet includes functional units configured to perform general-purpose graphics processing operations, and the third logic chiplet includes functional units configured to perform matrix acceleration operations; and
a memory coupled with the general-purpose graphics processor.
13. The data processing system as in claim 12 , wherein the one or more chiplets include a memory chiplet including memory cells associated with a memory device, the memory chiplet coupled to a first memory chiplet slot.
14. The data processing system as in claim 13 , wherein the one or more chiplets include a second logic chiplet.
15. The data processing system as in claim 14 , wherein the memory chiplet includes cache memory cells.
16. The data processing system as in claim 15 , wherein the second logic chiplet is coupled with the base die and connected to the interconnect fabric via a second interconnect structure, the second interconnect structure bonded to a second logic chiplet slot, wherein the second logic chiplet slot is configured to accept the second logic chiplet or a fourth logic chiplet, wherein the second logic chiplet includes functional units configured to perform media encode or decode operations and the fourth logic chiplet includes a network processor and a physical network interface.
17. The data processing system as in claim 16 , wherein each chiplet is independently power gated.
18. The data processing system as in claim 17 , wherein a logic chiplet includes a first layer including functional units and second layer including a fabric interconnect node.
19. The data processing system as in claim 18 , wherein a memory chiplet includes a first layer including a bank of memory cells and second layer including I/O circuits associated with an interconnect bridge between the memory chiplet and a logic chiplet.
20. The data processing system as in claim 12 , wherein the base die is a first base die and the first base die couples with a second base die via an interconnect bridge.