Input termination circuits for high speed receivers
The present invention is directed to communication systems and electrical circuits. According to an embodiment, an input termination circuit includes a first attenuation resistor and a second attenuation resistor. The resistance values of these two resistors are adjusted in opposite directions to maintain a stable output impedance. There are other embodiments as well.
1. A receiver apparatus comprising:
an input terminal configured to receive analog signal;
an input termination circuit, the input termination circuit comprising:
a first inductor connected to the input terminal;
a first input resistor connected to the first inductor;
a second input resistor connected to the first input resistor and the first inductor;
a second inductor connected to the first input resistor;
a first attenuation resistor connected to the first input resistor and the second inductor, the first attenuation resistor being adjustable by a first control signal;
an output inductor connected to the second inductor, the output inductor being associated with an output bandwidth;
a second attenuation resistor connected to the second inductor and the output inductor, the second attenuation resistor being adjustable by a second control signal; and
a continuous time linear equalizer (CTLE) coupled to the output inductor.
2. The apparatus of claim 1 further comprising a loss-of-signal detection (LOSD) module coupled to the input terminal.
3. The apparatus of claim 1 further comprising a variable gain amplifier coupled to the CTLE.
4. The apparatus of claim 1 further comprising a clock-and-data recovery (CDR) module.
5. The apparatus of claim 1 wherein the receiver is a SerDes receiver, the SerDes receiver comprising an analog front end.
6. The apparatus of claim 1 wherein the input terminal circuit is characterized by an output impedance matching an input impedance of the CTLE.
7. A method of adjusting an input termination circuit, wherein the input termination circuit comprising a first attenuation resistor and a second attenuation resistor, the method comprising:
initiating attenuation parameters associated with the input termination circuit, the attenuation parameters including a first resistance value associated with the first attenuation resistor and a second resistance value associated with the second attenuation resistor;
determining an attenuation setting;
adjusting the first resistance value based at least on the attenuation setting;
adjusting the second resistance value based on the first resistance value and the attenuation setting;
determining a bandwidth associated with the input termination circuit;
adjusting the second resistance value until the bandwidth reaches a desired level; and
receiving data signals using the input termination circuit.
8. The method of claim 7 further comprising generating control signals for adjusting the first resistance value and the second resistance value.
9. The method of claim 7 further comprising adjusting a resistance value of an input resistor.