Method and apparatus for camouflaging an integrated circuit using virtual camouflage cells

1. A computer-implemented method of camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a circuit comprising a plurality of interconnected functional logic cells performing a logical function, the method comprising steps of:

accepting a coded description of the circuit, wherein the coded description describes the circuit in terms of components comprising a sequential logic component and a virtual camouflage component;

generating a logical description of the circuit, the logical description of the circuit comprising a logical description of the virtual camouflage component; and

replacing, in the logical description of the circuit, the logical description of the virtual camouflage component with a logical description of a functionally equivalent technology-dependent camouflaged component.

2. The method of claim 1 , wherein:

the generating a logical description of the circuit comprises:

generating a technology specific pre-replacement netlist of gate-level components of the circuit including a logical model of the virtual camouflage component; and

the replacing, in the logical description of the circuit, the logical description of the virtual camouflage component with a logical description of a functionally equivalent technology-dependent camouflaged component comprises:

replacing, in the technology specific pre-replacement netlist of gate-level components, the logical model of the virtual camouflage component with a gate-level model of the functionally equivalent technology-dependent camouflaged component.

3. The method of claim 2 , wherein:

the generating the logical description of the circuit comprises any one or more of a logic synthesis, restructuring, and optimization of the coded description of the circuit; and

the virtual camouflage component has an attribute that excludes the virtual camouflage component from the any one or more of the logic synthesis, restructuring, and optimization of the coded description of the circuit.

4. The method of claim 3 , wherein:

the virtual camouflage component is selected from a virtual camouflage cell library (VCL), the VCL having a plurality of VCL cells including at least one of a driven VCL cell and an undriven VCL cell.

5. The method of claim 4 , wherein:

the virtual camouflage component is a driven VCL cell;

the replacing, in the technology specific pre-replacement netlist, the logical model of the virtual camouflage component with a gate-level model of the functionally equivalent technology-dependent camouflaged component comprises:

swapping, via an automated netlist editing program, the logical model of the virtual camouflage component with the gate-level model of the functionally equivalent technology-dependent camouflaged component;

identifying unconnected don't-care inputs of the functionally equivalent technology-dependent camouflaged component; and

connecting the unconnected don't care inputs to additional nodes within the circuit.

6. The method of claim 4 , wherein:

the virtual camouflage component is an undriven VCL cell;

the ASIC comprises an original driver output communicatively coupled to an original load of the ASIC and a camouflaged input of the undriven VCL cell;

the replacing, in the technology specific pre-replacement netlist, the logical model of the virtual camouflage component with a gate-level model of the functionally equivalent technology-dependent camouflaged component comprises:

disconnecting, via an automated netlist editing program, the original driver output from the original loads of the ASIC;

instantiating, via the automated netlist editing program, a merging logic gate having a first input, a second input and an output;

connecting, via the automated netlist editing program, the output of the functionally equivalent technology-dependent camouflaged component to the first input of the merging logic gate;

connecting, via the automated netlist editing program, the original driver output to the second input of the merging logic gate; and

connecting, via the automated netlist editing program, the output of the merging logic gate to the original loads of the ASIC.

7. The method of claim 6 , wherein the functionally equivalent technology-dependent camouflaged component drives a drain voltage VDD and wherein the merging logic gate comprises and AND2 gate or an XNOR2 gate.

8. The method of claim 6 , wherein the functionally equivalent technology-dependent camouflaged component drives a source voltage VSS and wherein the merging logic gate comprises an OR2 gate or an XOR2 gate.

9. The method of claim 6 , further comprising:

connecting, via the automated netlist editing program, don't-care inputs of the undriven VCL cell to other nodes of the ASIC.

10. The method of claim 1 , wherein the coded description of the circuit of the ASIC is a register transfer level (RTL) coded description of the ASIC.

11. An apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a circuit comprising a plurality of interconnected functional logic cells performing a logical function, the apparatus comprising:

a processor;

a memory, communicatively coupled to the processor, the memory storing processor instructions comprising instructions for:

accepting a coded description of the circuit, wherein the coded description describes the circuit in terms of components comprising sequential logic components and combinatorial logic components, and at least one virtual camouflage component;

generating a logical description of the circuit, the logical description of the circuit comprising a logical description of said at least one virtual camouflaged component; and

replacing, in the logical description of the circuit, the logical description of said at least one virtual camouflaged component with a logical description of a functionally equivalent technology-dependent camouflaged component.

12. The apparatus of claim 11 , wherein:

the instructions for generating a logical description of the circuit comprise:

instructions for generating a technology-specific pre-replacement netlist of gate-level components of the circuit including a logical model of the virtual camouflage component; and

the instructions for replacing, in the logical description of the circuit, the logical description of the virtual camouflage component with a logical description of a functionally equivalent technology-dependent camouflaged component comprises:

instructions for replacing, in the technology specific pre-replacement netlist of gate-level components, the logical model of the virtual camouflage component with a gate-level model of the functionally equivalent technology-dependent camouflaged component.

13. The apparatus of claim 12 , wherein:

the generating the logical description of the circuit comprises any one or more of a logic synthesis, restructuring, and optimization of the coded description of the circuit; and

the virtual camouflage component has an attribute that excludes the virtual camouflage component from the any one or more of the logic synthesis, restructuring, and optimization of the coded description of the circuit.

14. The apparatus of claim 13 , wherein:

the virtual camouflage component is selected from a virtual camouflage cell library (VCL), the VCL having a plurality of VCL cells including at least one of a driven VCL cell and an undriven VCL cell.

15. The apparatus of claim 14 , wherein:

the virtual camouflage component is a driven VCL cell;

the instructions for replacing, in the technology specific pre-replacement netlist, the logical model of the virtual camouflage component with a gate-level model of the functionally equivalent technology-dependent camouflaged component comprise instructions for:

swapping, via an automated netlist editing program, the logical model of the virtual camouflage component with the gate-level model of the functionally equivalent technology-dependent camouflaged component;

identifying unconnected don't-care inputs of the functionally equivalent technology-dependent camouflaged component; and

connecting the unconnected don't care inputs to additional nodes within the circuit.

16. The apparatus of claim 14 , wherein:

the virtual camouflage component is an undriven VCL cell;

the ASIC comprises original driver output communicatively coupled to an original load of the ASIC and a camouflaged input of the undriven VCL cell;

the instructions for the replacing, in the technology specific pre-replacement netlist, the logical model of the virtual camouflage component with a gate-level model of the functionally equivalent technology-dependent camouflaged component comprise instructions for:

disconnecting, via an automated netlist editing program, the original driver output from the original loads of the ASIC;

instantiating, via the automated netlist editing program, a merging logic gate having a first input, a second input and an output;

connecting, via the automated netlist editing program, an output of the functionally equivalent technology-dependent camouflaged component to the first input of the merging logic gate;

connecting, via the automated netlist editing program, the original driver output to the second input of the merging logic gate; and

connecting, via the automated netlist editing program, the output of the merging logic gate to the original loads of the ASIC.

17. The apparatus of claim 16 , wherein the functionally equivalent technology-dependent camouflaged component drives a drain voltage VDD and wherein the merging logic gate comprises and AND2 gate or an XNOR2 gate.

18. The apparatus of claim 16 , wherein the functionally equivalent technology-dependent camouflaged component drives a source voltage VSS and wherein the merging logic gate comprises an OR2 gate or an XOR2 gate.

19. The apparatus of claim 16 , further comprising:

connecting, via the automated netlist editing program, don't-care inputs of the undriven VCL cell to other nodes of the ASIC.

20. The apparatus of claim 11 , wherein the coded description of the circuit of the ASIC is a register transfer level (RTL) coded description of the ASIC.

21. An apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a circuit comprising a plurality of interconnected functional logic cells performing a logical function, the apparatus comprising:

means for accepting a coded description of the circuit, wherein the coded description describes the circuit in terms of components comprising sequential logic components and combinatorial logic components, and includes at least one virtual camouflage component;

means for generating a logical description of the circuit, the logical description of the circuit comprising a logical description of the virtual camouflage component; and

means for replacing, in the logical description of the circuit, the logical description of the virtual camouflage component with a logical description of a functionally equivalent technology-dependent camouflaged component.