Simultaneous bidirectional serial link interface with optimized hybrid circuit
An integrated circuit (IC) chip includes transceiver circuitry. The transceiver circuitry includes a differential transmit circuit and a hybrid circuit. The differential transmit circuit includes a first transmit path for transmitting first data of a first polarity to a transmission line. A second transmit path generates replica first data having a second polarity opposite the first polarity. The hybrid circuit includes a first input path coupled to the second transmit path. A second input path is coupled to the transmission line for receiving a first summed signal including the first data and second data. The second data is received from the transmission line simultaneous with transmission of the first data along the transmission line. An output circuit generates an output representing a summation of the replica first data and the first summed signal.
1. An integrated circuit (IC) chip, comprising:
transceiver circuitry, the transceiver circuitry including
a differential transmit circuit including
a first transmit path for transmitting first data of a first polarity to a transmission line,
a second transmit path for generating replica first data having a second polarity opposite the first polarity; and
a hybrid circuit including
a first input path coupled to the second transmit path,
a second input path coupled to the transmission line for receiving a first summed signal including the first data and second data, the second data received from the transmission line simultaneous with transmission of the first data along the transmission line, and
an output circuit to generate an output representing a summation of the replica first data and the first summed signal.
2. The IC chip of claim 1 , wherein the first transmit path includes an impedance for driving the first data onto the transmission line.
3. The IC chip of claim 1 , wherein the first input path includes a resistor divider network.
4. The IC chip of claim 3 , wherein the resistor divider network includes:
a hybrid resistor in series with a replica termination resistor.
5. The IC chip of claim 4 , wherein:
the hybrid resistor exhibits a first resistance that substantially matches a second resistance exhibited by the replica termination resistor.
6. The IC chip of claim 4 , wherein:
the replica termination resistor exhibits an infinite resistance.
7. The IC chip of claim 3 , wherein:
the resistor divider network is selectively tied to a fixed reference voltage.
8. The IC chip of claim 1 , further comprising:
receiver circuitry having a receiver input to receive the output from the output circuit.
9. A SerDes transceiver circuit, comprising:
a first simultaneous bidirectional transceiver for coupling to a first signaling link;
a second simultaneous bidirectional transceiver for coupling to a second signaling link, the first and second simultaneous bidirectional transceivers forming a dual-duplex configuration; and
wherein each of the first and second simultaneous bidirectional transceivers includes
a differential transmit circuit including
a first transmit path for transmitting first data of a first polarity to a transmission line,
a second transmit path for generating replica first data having a second polarity opposite the first polarity; and
a hybrid circuit including
a first input path coupled to the second transmit path,
a second input path coupled to the transmission line for receiving a first summed signal including the first data and second data, the second data received from the transmission line simultaneous with transmission of the first data along the transmission line, and
an output circuit to generate an output representing a summation of the replica first data and the first summed signal.
10. The SerDes transceiver circuit of claim 9 , wherein the first transmit path includes an impedance for driving the first data onto the transmission line.
11. The SerDes transceiver circuit of claim 9 , wherein the first input path includes a resistor divider network.
12. The SerDes transceiver circuit of claim 11 , wherein the resistor divider network includes:
a hybrid resistor in series with a replica termination resistor.
13. The SerDes transceiver circuit of claim 12 , wherein:
the hybrid resistor exhibits a first resistance that substantially matches a second resistance exhibited by the replica termination resistor.
14. The SerDes transceiver circuit of claim 12 , wherein:
the replica termination resistor exhibits an infinite resistance.
15. The SerDes transceiver circuit of claim 11 , wherein:
the resistor divider network is selectively tied to a fixed reference voltage.
16. The SerDes transceiver circuit of claim 9 , further comprising:
receiver circuitry having a receiver input to receive the output from the output circuitry.
17. A method of operation in a SerDes integrated circuit (IC) chip, comprising:
transmitting first data of a first polarity along a first transmit path to a transmission line,
generating replica first data having a second polarity opposite the first polarity; and
receiving second data from the transmission line simultaneously with transmitting the first data, the receiving including
receiving a first summed signal including the first data and the second data, and
generating an output representing a summation of the replica first data and the first summed signal.