Semiconductor device and manufacturing method thereof
In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.
1. A semiconductor device comprising:
a first fin structure disposed over a substrate;
an isolation insulating layer disposed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer;
a gate structure disposed over a part of the upper portion of the first fin structure;
a first source/drain (S/D) epitaxial layer disposed over the first fin structure not covered by the gate structure; and
a cap epitaxial layer formed over the first S/D epitaxial layer, wherein:
the first S/D epitaxial layer includes SiP, and
the cap epitaxial layer includes SiC or SiCP with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.
2. The semiconductor device of claim 1 , wherein a thickness of the cap epitaxial layer is in a range from 0.5 nm to 5 nm.
3. The semiconductor device of claim 1 , wherein a concentration of phosphorous in the SiP of the first S/D epitaxial layer is in a range from 5 atomic % to 20 atomic %.
4. The semiconductor device of claim 1 , wherein the cap epitaxial layer includes SiC with the carbon concentration being in a range from 1 atomic % to 3 atomic %.
5. The semiconductor device of claim 1 , further comprising an S/D contact in contact with the cap epitaxial layer.
6. The semiconductor device of claim 5 , further comprising an interlayer dielectric (ILD) layer disposed over the isolation insulating layer,
wherein the S/D contact is embedded in the ILD layer.
7. The semiconductor device of claim 6 , wherein the cap epitaxial layer is in direct contact with the ILD layer.
8. The semiconductor device of claim 1 , wherein the fin structure is a recessed fin structure of which upper surface is located below an upper surface of the isolation insulating layer.
9. A semiconductor device comprising:
a first fin structure disposed over a substrate;
a second fin structure disposed over the substrate;
an isolation insulating layer disposed over the substrate such that an upper portion of the first fin structure and an upper portion of the second fin structure protrude from the isolation insulating layer;
a first source/drain (S/D) epitaxial layer disposed over an S/D region of the first fin structure;
a cap epitaxial layer formed over the first S/D epitaxial layer; and
a second S/D epitaxial layer disposed over an S/D region of the second fin structure, wherein:
the first S/D epitaxial layer includes SiP, and
the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.
10. The semiconductor device of claim 9 , wherein the second S/D epitaxial layer includes Ge or SiGe with a Ge concentration being in a range from 10 atomic % to 90 atomic %.
11. The semiconductor device of claim 10 , wherein no Ge containing layer is disposed on at least a part of the cap epitaxial layer.
12. The semiconductor device of claim 9 , wherein a thickness of the cap epitaxial layer is in a range from 0.5 nm to 5 nm.
13. The semiconductor device of claim 9 , wherein a concentration of phosphorous in the SiP of the first S/D epitaxial layer is in a range from 5 atomic % to 20 atomic %.
14. The semiconductor device of claim 9 , further comprising an S/D contact in contact with the cap epitaxial layer.
15. The semiconductor device of claim 9 , further comprising an interlayer dielectric (ILD) layer disposed over the isolation insulating layer,
wherein the S/D contact is embedded in the ILD layer.
16. The semiconductor device of claim 9 , wherein the second S/D epitaxial layer includes SiP, and the first S/D epitaxial layer and the second S/D epitaxial layer are merged forming a merged epitaxial layer, and
the cap epitaxial layer is disposed over the merged epitaxial layer.
17. A semiconductor device including a static random access memory (SRAM) cell, the SRAM cell comprising:
first fin structures for n-channel fin field effect transistors (FinFETs) disposed over a substrate;
a second fin structure for p-channel FinFET disposed over the substrate;
an isolation insulating layer disposed over the substrate such that upper portions of the first fin structures and an upper portion of the second fin structure protrude from the isolation insulating layer;
a gate electrode disposed over the first fin structures and the second fin structure;
first source/drain (S/D) epitaxial layers disposed over the first fin structures;
a cap epitaxial layer disposed over the first S/D epitaxial layers;
a second S/D epitaxial layer disposed over the second fin structure, wherein:
the first S/D epitaxial layers include SiP,
the cap epitaxial layer includes SiC or SiCP, and
the cap epitaxial layer has a carbon concentration being in a range from 0.5 atomic % to 5 atomic %.
18. The semiconductor device of claim 17 , wherein a concentration of phosphorous in the SiP of the first S/D epitaxial layers is in a range from 5 atomic % to 20 atomic %.
19. The semiconductor device of claim 17 , wherein the second S/D epitaxial layer includes Ge or SiGe, and an amount of Ge on the cap epitaxial layers is less than 10×10 14 atoms/cm 3 .
20. The semiconductor device of claim 19 , wherein the second S/D epitaxial layer includes Ge or SiGe, and no Ge containing layer is disposed on the cap epitaxial layer.