Systems, methods, and devices for fast wakeup of DC-DC converters including feedback regulation loops
Systems, methods, and devices implement direct current (DC)-DC converters having fast wake up times and low ripple effects. Methods include determining a DC-DC converter is to be transitioned from an operational mode to a low power mode, and storing a voltage at an input of a comparator coupled to an input of a charge pump, the voltage being stored in a feedback capacitor of a feedback regulation loop. The methods further include uncoupling a voltage trimming circuit from the input of the comparator, and maintaining, at least in part, the stored voltage at the feedback capacitor during the low power mode.
1. A method comprising:
determining a direct current (DC)-DC converter is to be transitioned from an operational mode to a low power mode;
storing a voltage at an input of a comparator coupled to an input of a charge pump, the voltage being stored in a feedback capacitor of a feedback regulation loop;
uncoupling a voltage trimming circuit from the input of the comparator; and
maintaining, at least in part, the stored voltage at the feedback capacitor during the low power mode such that the stored voltage is available at the input of the comparator which provides an output to the charge pump to enable the charge pump during a subsequent transition from the low power mode to the operational mode.
2. The method of claim 1 further comprising:
discharging the voltage trimming circuit to a circuit ground (GND) during the low power mode; and
disabling the comparator during the low power mode.
3. The method of claim 1 further comprising:
determining the DC-DC converter is to be transitioned from the low power mode to the operational mode;
operating the comparator based on the voltage stored in the feedback capacitor to the comparator; and
coupling the voltage trimming circuit to the comparator.
4. The method of claim 3 , wherein the voltage stored in the feedback capacitor identifies a differential voltage across the feedback capacitor that is determined based on a difference between the voltage trimming value determined at a time of the storing, and an output voltage of the charge pump.
5. The method of claim 3 , wherein the coupling of the voltage trimming circuit to the comparator occurs after a designated delay.
6. The method of claim 5 , wherein an output voltage of the voltage trimming circuit stabilizes during the designated delay, and wherein the charge pump transitions from the low power mode to the operational mode prior to the output voltage of the voltage trimming circuit stabilizing.
7. The method of claim 3 , wherein the coupling and decoupling are implemented using a switch.
8. The method of claim 1 , wherein the DC-DC converter is implemented in a voltage supply block of a nonvolatile memory.
9. A device comprising:
a charge pump;
a voltage trimming circuit;
a feedback regulation loop coupled to the charge pump, the feedback regulation loop comprising:
a comparator comprising an output, a first input, and a second input, the output being coupled to an input of the charge pump;
a feedback capacitor comprising a first node and a second node, the first node being coupled to an output of the charge pump, and the second node being coupled to the first input of the comparator, the feedback capacitor being configured to store a voltage that is available at an input of the comparator which provides an output to the charge pump to enable the charge pump during a transition from a low power mode to an operational mode; and
a switch coupled between an output of the voltage trimming circuit and the second node of the feedback capacitor, wherein in the low power mode, the switch is configured to uncouple the voltage trimming circuit from the feedback regulation loop, and wherein in the operational mode, the switch is configured to couple the voltage trimming circuit with the feedback regulation loop.
10. The device of claim 9 , wherein when transitioning from the low power mode to the operational mode, the switch is configured to couple the voltage trimming circuit with the feedback regulation loop after a designated delay.
11. The device of claim 10 , wherein the output voltage of the voltage trimming circuit stabilizes during the designated delay, and wherein the charge pump transitions from the low power mode to the operational mode prior to the output voltage of the voltage trimming circuit stabilizing.
12. The device of claim 9 , wherein the voltage stored in the feedback capacitor represents a differential voltage across the feedback capacitor that is determined based on a difference between a voltage trimming value and an output voltage of the charge pump.
13. The device of claim 9 , wherein the voltage trimming circuit is configured to be discharged to ground (GND) during the low power mode, and wherein the comparator is configured to be disabled during the low power mode.
14. The device of claim 9 , wherein the second input of the comparator is coupled to a reference voltage.
15. The device of claim 9 , wherein the voltage trimming circuit comprises a diode stack.
16. The device of claim 9 , wherein the device is a DC-DC converter included in a voltage supply block of a nonvolatile memory.
17. A system comprising:
a nonvolatile memory;
a voltage supply block comprising:
a charge pump;
a voltage trimming circuit;
a feedback regulation loop coupled to the charge pump, the feedback regulation loop comprising:
a comparator comprising an output, a first input, and a second input, the output being coupled to an input of the charge pump;
a feedback capacitor comprising a first node and a second node, the first node being coupled to an output of the charge pump, and the second node being coupled to the first input of the comparator, the feedback capacitor being configured to store a voltage that is available at an input of the comparator which provides an output to the charge pump to enable the charge pump during a transition from a low power mode to an operational mode; and
a switch coupled between an output of the voltage trimming circuit and the second node of the feedback capacitor, wherein in the low power mode, the switch is configured to uncouple the voltage trimming circuit from the feedback regulation loop, and wherein in the operational mode, the switch is configured to couple the voltage trimming circuit with the feedback regulation loop.
18. The system of claim 17 , wherein when transitioning from the low power mode to the operational mode, the switch is configured to couple the voltage trimming circuit with the feedback regulation loop after a designated delay, wherein the output voltage of the voltage trimming circuit stabilizes during the designated delay, and wherein the charge pump transitions from the low power mode to the operational mode prior to the output voltage of the voltage trimming circuit stabilizing.
19. The system of claim 17 , wherein the voltage stored in the feedback capacitor identifies a voltage trimming value.
20. The system of claim 17 , wherein the voltage trimming circuit is configured to be discharged to ground (GND) during the low power mode, and wherein the comparator is configured to be disabled during the low power mode.