Ultra-low power adaptively reconfigurable system

1. An apparatus comprising:

an input/output (IO) device to receive a first input signal; and

a programmable analog subsystem (PASS) coupled to the IO device, wherein the PASS comprises:

a plurality of reconfigurable analog circuits, comprising at least one of:

a continuous time block (CTB), or

an analog-to-digital converter (ADC);

a logic circuit; and

an interface to communicate data with a central processing unit (CPU) external to the PASS,

wherein the PASS is configured to:

in a first PASS configuration, process the first input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the first input signal, the plurality of reconfigurable analog circuits having a first configuration setting in the first PASS configuration; and

change, responsive to the logic circuit processing the first output value, one or more settings of the CTB to reconfigure the PASS into a second PASS configuration with a second configuration setting, wherein the second configuration setting is different than the first configuration setting.

2. The apparatus of claim 1 , wherein the plurality of reconfigurable analog circuits have a higher operating power in the second PASS configuration than in the first PASS configuration.

3. The apparatus of claim 1 , wherein the PASS is further configured to:

in the second PASS configuration, process a second input signal through the plurality of reconfigurable analog circuits to generate a second output value, the plurality of reconfigurable analog circuits having the second configuration setting in the second PASS configuration; and

responsive to the second output value, output, through the interface, a wake-up signal to the CPU.

4. The apparatus of claim 3 , wherein the PASS is further configured to:

responsive to outputting the wake-up signal to the CPU, receive, from the CPU, configuration data comprising a third configuration setting, wherein the third configuration setting is different than the second configuration setting; and

reconfigure the plurality of reconfigurable analog circuits into a third PASS configuration with the third configuration setting.

5. The apparatus of claim 1 , wherein the PASS is further configured to:

in the second PASS configuration, process a second input signal through the plurality of reconfigurable analog circuits to generate a second output value, the plurality of reconfigurable analog circuits having the second configuration setting in the second PASS configuration; and

responsive to the second output value, output, through the interface, a mode selection signal to the CPU.

6. The apparatus of claim 1 , wherein the PASS comprises a first set of registers to store the first configuration setting and a second set of registers to store the second configuration setting.

7. The apparatus of claim 1 , wherein the PASS comprises a set of registers to store the first configuration setting, and wherein to reconfigure the plurality of reconfigurable analog circuits into the second configuration is to:

modify contents of the set of registers to store the second configuration setting; and

reconfigure at least one of the reconfigurable analog circuits according to the modified contents of the set of registers.

8. The apparatus of claim 1 , wherein the PASS is further to, responsive to the first output value, reconfigure: the analog-to-digital converter (ADC) circuit configured to process an output of the CTB; and one or more multiplexers configured to selectively connect a plurality of pins of the IO device to a plurality of inputs of at least of one of the CTB or the ADC circuit.

9. The apparatus of claim 8 , wherein the reconfigurable analog circuits further comprise at least one of:

an analog reference block to provide at least one of a voltage reference, a current reference, or a clock signal; or

a finite state machine having a plurality of states selectable according to an output of the PASS logic circuit.

10. A system comprising:

an input/output (IO) device to receive a first input signal from a signal source;

a digital subsystem comprising a memory and a central processing unit (CPU) coupled to the memory;

a programmable analog subsystem (PASS) coupled to the IO device and to the digital subsystem, wherein the PASS comprises:

a plurality of reconfigurable analog circuits, comprising at least one of:

a continuous time block (CTB), or

an analog-to-digital converter (ADC);

a logic circuit; and

an interface to communicate data with the CPU external to the PASS,

wherein the PASS is configured to:

in a first PASS configuration and with the digital subsystem in a sleep mode, process the first input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the first input signal, the plurality of reconfigurable analog circuits having a first configuration setting in the first PASS configuration; and

change, responsive to the logic circuit processing the first output value, one or more settings of the CTB to reconfigure the PASS into a second PASS configuration with a second configuration setting without CPU involvement, wherein the second configuration setting is different than the first configuration setting.

11. The system of claim 10 , wherein the plurality of reconfigurable analog circuits have a higher operating power in the second PASS configuration than in the first PASS configuration.

12. The system of claim 10 , wherein the PASS is further configured to:

in the second PASS configuration, process a second input signal through the plurality of reconfigurable analog circuits to generate a second output value, the plurality of reconfigurable analog circuits having the second configuration setting in the second PASS configuration; and

responsive to the second output value, output, through the interface, a mode selection signal to the digital subsystem.

13. The system of claim 12 , wherein the PASS is further configured to:

responsive to outputting the mode selection signal to the digital subsystem, receive, from the digital subsystem, configuration data comprising a third configuration setting, wherein the third configuration setting is different than the second configuration setting; and

reconfigure the plurality of reconfigurable analog circuits into a third PASS configuration with the third configuration setting.

14. The system of claim 10 , wherein the PASS comprises a first set of registers to store the first configuration setting and a second set of registers to store the second configuration setting.

15. The system of claim 10 , wherein the PASS comprises a set of registers to store the first configuration setting, and wherein to reconfigure the plurality of reconfigurable analog circuits into the second configuration is to:

modify contents of the set of registers to store the second configuration setting; and

reconfigure at least one of the reconfigurable analog circuits according to the modified contents of the set of registers.

16. A method comprising:

receiving a first input signal from an input/output (IO) device by a programmable analog subsystem (PASS) coupled to the IO device, the PASS comprising a plurality of reconfigurable analog circuits, the plurality of reconfigurable analog circuits comprising at least one of (i) a continuous time block (CTB) or (ii) an analog-to-digital converter (ADC), a logic circuit, and an interface to communicate data with a central processing unit (CPU) external to the PASS;

processing, with the PASS in a first PASS configuration, the first input signal through the plurality of reconfigurable analog circuits, wherein the plurality of reconfigurable analog circuits have a first configuration setting in the first PASS configuration;

generating a first output value based on the first input signal; and

changing, responsive to the logic circuit processing the first output value, one or more settings of the CTB to reconfigure functionality of the plurality of reconfigurable analog circuits into a second PASS configuration with a second configuration setting, wherein the second configuration setting is different than the first configuration setting.

17. The method of claim 16 , wherein the plurality of reconfigurable analog circuits have a higher operating power in the second PASS configuration than in the first PASS configuration.

18. The method of claim 16 , wherein reconfiguring the plurality of reconfigurable analog circuits into the second PASS configuration is responsive to determining that the first output value meets a first threshold criteria.

19. The method of claim 16 , further comprising:

processing, with the PASS in the second PASS configuration, a second input signal through the plurality of reconfigurable analog circuits, wherein the plurality of reconfigurable analog circuits have the second configuration setting in the second PASS configuration;

generating a second output value; and

responsive to the second output value, outputting, through the interface, a signal to the CPU.

20. The method of claim 19 , wherein outputting the signal to the CPU is responsive to determining that the second output value meets a second threshold criteria.

21. The method of claim 19 , further comprising

responsive to outputting the signal to the CPU, receiving, from the CPU, configuration data comprising a third configuration setting, wherein the third configuration setting is different than the second configuration setting; and

reconfiguring the plurality of reconfigurable analog circuits into a third PASS configuration with the third configuration setting.

22. The method of claim 19 , wherein the PASS comprises a first set of registers to store the first configuration setting and a second set of registers to store the second configuration setting.

23. The method of claim 19 , wherein the PASS comprises a set of registers to store the first configuration setting, and wherein reconfiguring the plurality of reconfigurable analog circuits into the second configuration comprises:

modifying contents of the set of registers to store the second configuration setting; and

reconfiguring at least one of the reconfigurable analog circuits according to the modified contents of the set of registers.