Hall sensor with performance control
A Hall sensor includes a Hall well, such as an implanted region in a surface layer of a semiconductor structure, and four doped regions spaced apart from one another in the implanted region. The implanted region and the doped regions include majority carriers of the same conductivity type. The sensor also includes a dielectric layer that extends over the implanted region, and an electrode layer over the dielectric layer to operate as a control gate to set or adjust the sensor performance. A first supply circuit provides a first bias signal to a first pair of the terminals, and a second supply circuit provides a second bias signal to the electrode layer.
1. A semiconductor device, comprising:
a semiconductor structure, including:
an epitaxial layer over a semiconductor substrate, the epitaxial layer including a semiconductor surface layer having a first conductivity type, a first buried layer having an opposite second conductivity type and a second buried layer having the first conductivity type between the semiconductor surface layer and the first buried layer, and
an implanted region in the semiconductor surface layer, the implanted region touching the second buried layer and having the second conductivity type and a first dopant concentration;
first, second, third, and fourth terminals that electrically contact the implanted region at respective first, second, third, and fourth locations spaced apart from one another, each of the first, second, third, and fourth terminals including a corresponding first doped portion having the second conductivity type and a second dopant concentration in a corresponding second doped portion having the second conductivity type and a third dopant concentration greater than the first dopant concentration, the second dopant concentration greater than the third dopant concentration and the implanted region extending directly between the second doped portions and the second buried layer;
a dielectric layer that touches the implanted region and the second doped portions; and
an electrode layer that touches the dielectric layer and extends over the second doped portions.
2. The semiconductor device of claim 1 , wherein the first, second, third, and fourth terminals are located at corners of a square.
3. The semiconductor device of claim 1 , wherein the first, second, third, and fourth terminals further include respective first, second, third, and fourth contacts that electrically contact the respective first, second, third, and fourth doped regions.
4. The semiconductor device of claim 1 , wherein the dielectric layer has a non-zero thickness of 1200 Å (120 nm) or less.
5. The semiconductor device of claim 4 , wherein the thickness of the dielectric layer is 20 Å (2 nm) or more.
6. The semiconductor device of claim 4 , wherein the thickness of the dielectric layer is in a range from 20 Å (2 nm) to 200 Å (20 nm).
7. The semiconductor device of claim 1 , wherein the dielectric layer is in contact with the implanted region, and wherein the electrode layer is in contact with the dielectric layer.
8. The semiconductor device of claim 1 , further comprising:
a first supply circuit connected to provide a non-zero first bias signal between a first pair of the terminals; and
a second supply circuit connected to provide a non-zero second bias signal to the electrode layer.
9. The semiconductor device of claim 1 , wherein the electrode layer includes doped polysilicon with majority carriers of the first conductivity type.
10. The semiconductor device of claim 1 , wherein the electrode layer includes doped polysilicon with majority carriers of the second conductivity type.
11. The semiconductor device of claim 1 , wherein the first conductivity type is p-type, and wherein the second conductivity type is n-type.
12. The semiconductor device of claim 1 , wherein the first conductivity type is n-type, and wherein the second conductivity type is p-type.
13. A magnetic sensor, comprising:
an implanted region having a first conductivity type in a surface layer of a semiconductor structure;
a first buried semiconductor layer having the first conductivity type below the implanted region;
a second buried semiconductor layer having an opposite second conductivity type that is located between the first buried semiconductor layer and the implanted region and touches the implanted region;
first, second, third, and fourth doped regions spaced apart from one another in the implanted region, each doped region including a first doped portion within the implanted region and having a higher majority carrier concentration than the implanted region, and each doped region including a second doped portion within the first doped portion and having a higher majority carrier concentration than the first doped portion, the implanted region and the doped regions including majority carriers of the same conductivity type, and the implanted region extending directly between the second buried semiconductor layer and the second doped portions;
a dielectric layer on the implanted region and the first doped portions, the dielectric layer having a thickness of 1200 Å (120 nm) or less;
an electrode layer on the dielectric layer, the electrode layer extending over the first, second, third, and fourth doped regions;
a first supply circuit connected to provide a non-zero first bias voltage across a first pair of the doped regions; and
a second supply circuit connected to provide a non-zero second bias voltage to the electrode layer.
14. The magnetic sensor of claim 13 , wherein the thickness of the dielectric layer is 20 Å (2 nm) or more and 200 Å (20 nm) or less.
15. The magnetic sensor of claim 13 , wherein the electrode layer includes doped polysilicon with majority carriers of a different conductivity type as the implanted region and the doped regions.
16. The magnetic sensor of claim 13 , wherein the first, second, third, and fourth doped regions are located at corners of a square.
17. A semiconductor device, comprising:
an epitaxial layer having a top surface and a first conductivity type over a semiconductor substrate;
a buried layer having an opposite second conductivity type between the epitaxial layer and the substrate;
a well region having the second conductivity type within the epitaxial layer;
first, second, third and fourth terminals that include respective first, second, third and fourth doped regions having the second conductivity type within the well region, the doped regions having a greater dopant concentration than the well region, each doped region intersecting the top surface of the epitaxial layer and being spaced apart along the top surface and laterally touching the well region on three sides, the well region extending directly between the buried layer and the first, second, third and fourth doped regions; and
a polysilicon layer over the well region and the doped regions, and a dielectric layer touching the doped regions and the polysilicon layer.
18. The semiconductor device of claim 17 , further comprising an isolation region that surrounds the well region and includes a conductive connection to the epitaxial layer.
19. The semiconductor device of claim 17 , wherein each of the doped regions has a fourth side that laterally touches a surrounding doped region having the first conductivity type that intersects the top surface of the epitaxial layer and surrounds the well region.