Method for programming a memory system
A memory system includes a plurality of memory cells, and the memory cells are multiple-level cells. The memory system performs program operations to program the memory cells. After each program operation, at least one threshold voltage test is performed to determine if threshold voltages of the memory cells are greater than the verification voltage. When the threshold voltage of a first memory cell is determined to be greater than a first verification voltage, the first memory cell will be inhibited from being programmed during the next program operation. When the threshold voltage of a second memory cell is determined to newly become greater than a second verification voltage, where the second verification voltage is greater than the first verification voltage, the second memory cell will be programmed again during the next program operation.
1. A method for programming a memory system, the memory system comprising a plurality of memory cells, the method comprising:
performing a plurality of program operations to program the plurality of memory cells;
after each of the plurality of program operations, performing at least one threshold voltage test to determine if threshold voltages of the plurality of memory cells are greater than at least one verification voltage;
when a threshold voltage of a first memory cell is determined to be greater than a first verification voltage corresponding to a first programming state, inhibiting the first memory cell from being programmed during a next program operation; and
when a second memory cell is to be programmed into a second programming state and a threshold voltage of the second memory cell is determined to newly become greater than a second verification voltage corresponding to the second programming state, keeping programming the second memory cell during a next program operation;
wherein:
the plurality of memory cells are multiple-level cells (MLC);
the first programming state is lower than a predetermined programming state; and
the second programming state is no lower than the predetermined programming state.
2. The method of claim 1 , wherein when the threshold voltage of the second memory cell is determined to newly become greater than the second verification voltage corresponding to the second programming state, keeping programming the second memory cell during the next program operation is:
when the threshold voltage of the second memory cell is determined to newly become greater than the second verification voltage corresponding to the second programming state and a predetermined number of program operations have been performed, keeping programming the second memory cell during the next program operation.
3. The method of claim 2 , further comprising:
before the predetermined number of program operations have been performed, when a threshold voltage of a third memory cell is determined to newly become greater than the second verification voltage, inhibiting the third memory cell from being programmed during a next program operation.
4. The method of claim 2 , further comprising:
when there are more than a target number of memory cells that have not passed corresponding threshold voltage tests, performing a next program operation.
5. The method of claim 1 , further comprising:
during a first program operation of the plurality of program operations, generating a first program pulse to program the plurality of memory cells; and
during a second program operation of the plurality of program operations after the first program operation, generating a second program pulse to program the plurality of memory cells;
wherein the second program pulse has a voltage greater than the first program pulse.
6. A memory system comprising:
a plurality of memory cells coupled to at least one word line; and
a control circuit coupled to the at least one word line, and configured to:
perform a plurality of program operations to program the plurality of memory cells by providing program voltages through the at least one word line;
perform at least one threshold voltage test to determine if threshold voltages of the plurality of memory cells are greater than at least one verification voltage after each of the plurality of program operations;
inhibit a first memory cell from being programmed during a next program operation when a threshold voltage of the first memory cell is determined to be greater than a first verification voltage corresponding to a first programming state; and
keep programming a second memory cell during a next program operation when the second memory cell is to be programmed into a second programming state and a threshold voltage of the second memory cell is determined to newly become greater than a second verification voltage corresponding to the second programming state;
wherein:
the plurality of memory cells are multiple-level cells (MLC);
the first programming state is lower than a predetermined programming state; and
the second programming state is no lower than the predetermined programming state.
7. The memory system of claim 6 , wherein the control circuit keeps programming the second memory cell during the next program operation when the threshold voltage of the second memory cell is determined to newly become greater than the second verification voltage corresponding to the second programming state while a predetermined number of program operations have been performed.
8. The memory system of claim 7 , wherein the control circuit is further configured to inhibit a third memory cell from being programmed during a next program operation when a threshold voltage of the third memory cell is determined to newly become greater than the second verification voltage and before the predetermined number of program operations have been performed.
9. The memory system of claim 7 , wherein the control circuit is further configured to performing a next program operation when there are more than a target number of memory cells that have not passed corresponding threshold voltage tests.
10. The memory system of claim 6 , wherein the control circuit is further configured to:
generate a first program pulse to program the plurality of memory cells during a first program operation of the plurality of program operations; and
generating a second program pulse to program the plurality of memory cells during a second program operation of the plurality of program operations after the first program operation;
wherein the second program pulse has a voltage greater than the first program pulse.