IP Library Patent Application 16371654
Patent Application
App. No. 16/371,654

DISTRIBUTIVE-DRIVING OF LIQUID CRYSTAL DISPLAY (LCD) PANEL

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
16/371,654
Abstract

A liquid crystal display (LCD) apparatus includes a color filter layer, a liquid crystal (LC) layer, and a pixel circuit layer. The color filter layer includes a plurality of color filters corresponding to an array of pixels arranged in M rows and N columns. The number of the color filters is k times of the number of the pixels. The LC layer is divided into a plurality of LC regions, each of which corresponds to a respective one of the color filters. The pixel circuit layer includes a plurality pixel circuits, each of which is configured to drive a respective one of the LC regions. The pixel circuit layer also includes xM gate lines and (k/x)N source lines, where x is a fraction larger than one, and each of xM and (k/x)N is a positive integer.

Claims (51)

1 . A liquid crystal display (LCD) apparatus, comprising:

a color filter layer comprising a plurality of color filters, wherein the color filters correspond to an array of pixels arranged in M rows and N columns, and a number of the color filters is k times of a number of the pixels;

a liquid crystal (LC) layer divided into a plurality of LC regions, wherein each of the LC regions corresponds to a respective one of the color filters; and

a pixel circuit layer comprising:

a plurality pixel circuits, wherein each of the pixel circuits is configured to drive a respective one of the LC regions, and

xM gate lines and (k/x)N source lines, wherein x is a fraction larger than one, and each of xM and (k/x)N is a positive integer.

2 . The apparatus of claim 1 , wherein a ratio between a first pitch of the (k/x)N source lines and a second pitch of the xM gate lines is about x 2 /k.

3 . The apparatus of claim 2 , wherein the ratio is larger than ½.

4 . The apparatus of claim 3 , wherein the ratio is about ¾ or 9/8.

5 . The apparatus of claim 1 , wherein:

the plurality of color filters are arranged in a repeating pattern; and

two adjacent rows of the color filters are staggered with each other.

6 . The apparatus of claim 5 , wherein two adjacent rows of the color filters are staggered with each other by one half of a height of each of the color filters.

7 . The apparatus of claim 5 , wherein each of the xM gate lines is a polyline.

8 . The apparatus of claim 1 , wherein:

the plurality of color filters are arranged in a repeating pattern; and

two adjacent columns of the color filters are staggered with each other.

9 . The apparatus of claim 8 , wherein two adjacent columns of the color filters are staggered with each other by one half of a height of each of the color filters.

10 . The apparatus of claim 8 , wherein each of the (k/x)N source lines is a polyline.

11 . The apparatus of claim 1 , wherein each of the pixel circuits has a same relative location with respect to a respective one of the color filters.

12 . The apparatus of claim 1 , wherein at least two of the pixel circuits have different relative locations with respect to their respective color filters.

13 . The apparatus of claim 1 , wherein a resolution of the LCD apparatus is N×M.

14 . The apparatus of claim 1 , further comprising:

a gate driving circuit operatively coupled to the pixel circuit layer via the xM gate lines and configured to scan the plurality of pixel circuits; and

a source driving circuit operatively coupled to the pixel circuit layer via the (k/x)N source lines and configured to write display data in a frame to the plurality of pixel circuits.

15 . The apparatus of claim 14 , wherein the display data in the frame comprises M×N pieces of pixel data, each piece of pixel data corresponding to one of the array of pixels and comprising a first component representing a first color, a second component representing a second color, and a third component representing a third color.

16 . The apparatus of claim 14 , further comprising control logic operatively coupled to the gate driving circuit and source driving circuit, the control logic comprising:

a data interface configured to receive original display data;

a data converting module configured to convert the original display data into converted display data based on the (k/x)N source lines; and

a control signal generating module configured:

provide a first set of control signals to the gate driving circuit to control the gate driving circuit to scan the plurality of pixel circuits via the xM gate lines, and

provide a second set of control signals to the source driving circuit to control the source driving circuit to write the converted display data to the plurality of pixel circuits.

17 . The apparatus of claim 1 , wherein

x is represented as p/q;

each of p and q is a positive integer; and

p is larger than q and is smaller than 2q.

18 . The apparatus of claim 17 , wherein x is 3/2.

19 . The apparatus of claim 1 , wherein each of the pixel circuits comprises a thin film transistor (TFT) and a capacitor.

20 . An LCD apparatus, comprising:

a color filter layer comprising a plurality of color filters, wherein the color filters correspond to an array of pixels arranged in M rows and N columns, and a number of the color filters is k times of a number of the pixels;

an LC layer divided into a plurality of LC regions, wherein each of the LC regions corresponds to a respective one of the color filters;

a pixel circuit layer comprising:

a plurality pixel circuits, wherein each of the pixel circuits is configured to drive a respective one of the LC regions, and

xM gate lines and (k/x)N source lines, wherein x is a fraction larger than one, and each of xM and (k/x)N is a positive integer;

a gate driving circuit operatively coupled to the pixel circuit layer via the xM gate lines and configured to scan the plurality of pixel circuits;

a source driving circuit operatively coupled to the pixel circuit layer via the (k/x)N source lines and configured to write display data in a frame to the plurality of pixel circuits; and

control logic operatively coupled to the gate driving circuit and source driving circuit and configured to:

receive original display data,

convert the original display data into converted display data based on the (k/x)N source lines,

provide a first set of control signals to the gate driving circuit to control the gate driving circuit to scan the plurality of pixel circuits via the xM gate lines, and

provide a second set of control signals to the source driving circuit to control the source driving circuit to write the converted display data to the plurality of pixel circuits.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2021
From: BEIJING YUNYINGGU TECHNOLOGY CO., LTD.
To: KUNSHAN YUNYINGGU ELECTRONIC TECHNOLOGY CO., LTD.
Reel/Frame 055262/0117 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2019
From: SHANGHAI YUNYINGGU TECHNOLOGY CO., LTD.
To: BEIJING YUNYINGGU TECHNOLOGY CO., LTD.
Reel/Frame 048791/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2019
From: GU, JING; PENG, YU-HSUN; TSENG, SHIH-WEI
To: SHANGHAI YUNYINGGU TECHNOLOGY CO., LTD.
Reel/Frame 048756/0360 →