System and method for improved storage access in multi core system
A system and method for improving multi-core processor access to storages, the method including: assigning a unique memory space within a memory to each of a plurality of processor cores; initiating a shared queue pair (QP), comprising a shared send queue and a shared receive queue, between the plurality of processor cores and at least a storage, wherein the shared queue is accessible by the plurality of processor cores; sending an instruction on the shared send queue from a first core of the plurality of processor cores to the storage, the instruction comprising an interrupt destination on a memory space assigned to the first core; and receiving an interrupt at the interrupt destination from the storage in response to the instruction, wherein the interrupt is generated for the first core.
1. A method for improving multi-core processor access to storages, the method comprising:
assigning a unique memory space within a memory to each of a plurality of processor cores;
initiating a shared queue pair (QP) between the plurality of processor cores and at least a storage, the shared QP comprising a shared send queue and a shared receive queue, wherein the shared QP is accessible by the plurality of processor cores;
sending an instruction on the shared send queue from a first core of the plurality of processor cores to the storage, the instruction comprising an interrupt destination on a memory space assigned to the first core; and
receiving an interrupt at the interrupt destination from the storage in response to the instruction, wherein the interrupt is generated for the first core.
2. The method of claim 1 , wherein the storage is any of a local storage and a remote storage.
3. The method of claim 2 , wherein the storage is a network storage accessible over a remote direct memory access (RDMA) network.
4. The method of claim 3 , wherein the shared QP is established between a network interface controller (NIC) connected to the network storage and the plurality of cores, the shared QP comprising the shared send queue and the shared receive queue.
5. The method of claim 1 , wherein the shared QP is a first QP, wherein the first QP is established between a first group of processing cores from among the plurality of processor cores and a first group of storages, wherein a second QP is established for a second group of processing cores from among the plurality of cores and a second group of storages.
6. The method of claim 1 , further comprising:
establishing a shared completion queue (CQ) between the plurality of cores and the storage, wherein the shared CQ is configured to send and receive indications that a request has been completed and that responses to the request have been received.
7. The method of claim 1 , wherein the instruction is any of a write instruction and a read instruction.
8. The method of claim 1 , wherein the interrupt destination further includes a data block address within the memory space assigned to the first core.
9. The method of claim 1 , wherein each unique memory space is assigned to one of the plurality of processor cores dynamically.
10. A non-transitory computer readable medium having stored thereon instructions for causing a processing circuitry to perform a process, the process comprising:
assigning a unique memory space within a memory to each of a plurality of processor cores;
initiating a shared queue pair (QP) between the plurality of processor cores and at least a storage, the shared QP comprising a shared send queue and a shared receive queue, wherein the shared QP is accessible by the plurality of processor cores;
sending an instruction on the shared send queue from a first core of the plurality of processor cores to the storage, the instruction comprising an interrupt destination on a memory space assigned to the first core; and
receiving an interrupt at the interrupt destination from the storage in response to the instruction, wherein the interrupt is generated for the first core.
11. A system for improving multi-core processor access to storages, comprising:
a processing circuitry; and
a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to:
assign a unique memory space within a memory to each of a plurality of processor cores;
initiate a shared queue pair (QP) between the plurality of processor cores and at least a storage, the shared QP comprising a shared send queue and a shared receive queue, wherein the shared QP is accessible by the plurality of processor cores;
send an instruction on the shared send queue from a first core of the plurality of processor cores to the storage, the instruction comprising an interrupt destination on a memory space assigned to the first core; and
receive an interrupt at the interrupt destination from the storage in response to the instruction, wherein the interrupt is generated for the first core.
12. The system of claim 11 , wherein the storage is any of a local storage and a remote storage.
13. The system of claim 12 , wherein the storage is a network storage accessible over a remote direct memory access (RDMA) network.
14. The system of claim 13 , wherein the shared QP is established between a network interface controller (NIC) connected to the network storage and the plurality of cores, the shared QP comprising the shared send queue and the shared receive queue.
15. The system of claim 11 , wherein the shared QP is a first QP, wherein the first QP is established between a first group of processing cores from among the plurality of processor cores and a first group of storages, wherein a second QP is established for a second group of processing cores from among the plurality of cores and a second group of storages.
16. The system of claim 11 , wherein the system if further configured to:
establish a shared completion queue (CQ) between the plurality of cores and the storage, wherein the shared CQ is configured to send and receive indications that a request has been completed and that responses to the request have been received.
17. The system of claim 11 , wherein the instruction is any of a write instruction and a read instruction.
18. The system of claim 11 , wherein the interrupt destination further includes a data block address within the memory space assigned to the first core.
19. The system of claim 11 , wherein each unique memory space is assigned to one of the plurality of processor cores dynamically.