Method and system for a feedback transimpedence amplifier with sub-40KHZ low-frequency cutoff
A system for a differential trans-impedance amplifier circuit comprising: an amplifier having a pair of input nodes and configured to generate an amplified replica of a differential voltage on said pair of input nodes; a photodiode; a pair of capacitors coupling said photodiode to said pair of input nodes; at least one resistance coupled between said pair of input nodes of said amplifier; and a bias network comprising two photodiode biasing resistances each photodiode biasing resistance coupled in series between said photodiode and a respective DC voltage. A feedback loop for the amplifier may include source followers that are operable to level shift voltages prior to coupling capacitors that couple said photodiode to said amplifier to ensure stable bias conditions for said amplifier. The source followers may include CMOS transistors. The amplifier may be integrated in a complementary metal-oxide semiconductor (CMOS) chip, which may include a CMOS photonics chip.
1. A system for processing electrical signals, the system comprising:
an amplifier circuit having coupling capacitors, a gain stage, and feedback paths comprising source follower transistors, wherein:
said feedback paths are coupled to first terminals of said coupling capacitors;
second terminals of said coupling capacitors are coupled to inputs of said gain stage;
said gain stage amplifies electrical signals received via said coupling capacitors; and
gate terminals of said source follower transistors are coupled to output terminals of said gain stage.
2. The system according to claim 1 , wherein said source follower transistors are operable to level shift voltages prior to said coupling capacitors to ensure stable bias conditions for said amplifier circuit.
3. The system according to claim 1 , wherein said amplifier circuit is integrated in a complementary metal-oxide semiconductor (CMOS) chip.
4. The system according to claim 3 , wherein said CMOS chip comprises a CMOS photonics chip.
5. The system according to claim 4 , wherein said CMOS photonics chip receives optical signals for said photodetector via one or more optical fibers.
6. The system according to claim 1 , wherein said source follower transistors comprise CMOS transistors.
7. The system according to claim 1 , wherein said gain stage receives current-mode logic signals.
8. The system according to claim 1 , wherein said gain stage receives voltage signals.
9. The system according to claim 1 , wherein said electrical signals are received from a photodetector.
10. The system according to claim 9 , wherein said photodetector comprises a silicon germanium photodiode.
11. The system according to claim 9 , wherein said photodetector is differentially coupled to said gain stage.
12. A method for processing optical signals, the method comprising:
in an amplifier circuit having coupling capacitors, a gain stage, and feedback paths comprising source follower transistors, wherein said feedback paths are coupled to first terminals of said coupling capacitors, second terminals of said coupling capacitors are coupled to inputs of said gain stage, and gate terminals of said source follower transistors are coupled to output terminals of said gain stage:
amplifying electrical signals received via said coupling capacitors utilizing said gain stage.
13. The method according to claim 12 , comprising level shifting voltages prior to said coupling capacitors to ensure stable bias conditions for said amplifier circuit.
14. The method according to claim 12 , wherein said source follower transistors comprise CMOS transistors.
15. The method according to claim 12 , wherein said gain stage receives current-mode logic signals.
16. The method according to claim 12 , wherein said gain stage receives voltage signals.
17. The method according to claim 12 , wherein said amplifier circuit is integrated in a complementary metal-oxide semiconductor (CMOS) chip.
18. The method according to claim 17 , wherein said CMOS chip comprises a CMOS photonics chip.
19. The method according to claim 12 , comprising receiving said electrical signals from a photodetector.
20. The method according to claim 19 , comprising receiving optical signals for said photodetector in said CMOS photonics chip via one or more optical fibers.
21. The method according to claim 19 , wherein said photodetector comprises a silicon germanium photodiode.
22. The method according to claim 19 , wherein said photodetector is differentially coupled to said gain stage.