Sub-device field-effect transistor architecture for integrated circuits
The present disclosure describes aspects of a sub-device field-effect transistor architecture for integrated circuits. In some aspects, an integrated field-effect transistor (FET) is implemented with multiple FET sub-devices. During operation, source-side FET sub-devices of the integrated FET may operate in the linear region instead of in saturation. Operating in the linear region, the source-side FET sub-devices of the integrated FET may exhibit less threshold voltage or current sensitivity than other drain-side FET sub-devices that operate in saturation. A device layout of the integrated FET may be designed such that the less sensitive source-side FET sub-devices surround or protect the other more sensitive drain-side FET sub-devices from random variations or density issues at edges of the device layout. By so doing, a threshold voltage or current sensitivity of the integrated FET may be reduced, resulting in improved matching between integrated FET devices.
1. A method of forming an integrated field-effect transistor (FET) of FET sub-devices, the method comprising:
forming a substrate for the integrated FET;
forming, on the substrate, a first set of the FET sub-devices, a first FET sub-device of the first set of the FET sub-devices coupled to a drain terminal of the integrated FET; and
forming, on the substrate, a second set of the FET sub-devices, a second FET sub-device of the second set of the FET sub-devices coupled to a source terminal of the integrated FET,
wherein (i) the first set of the FET sub-devices is formed on an interior portion of substrate area on which the integrated FET is formed and (ii) the second set of the FET sub-devices is formed proximate a perimeter of the substrate area on which the integrated FET is formed.
2. The method as recited in claim 1 , further comprising forming the second set of the FET sub-devices on a planar surface of the substrate area to surround the first set of the FET sub-devices on three sides.
3. The method as recited in claim 1 , further comprising forming the second set of the FET sub-devices on a planar surface of the substrate area to surround the first set of the FET sub-devices on all sides.
4. The method as recited in claim 1 , further comprising forming a gate terminal of the integrated FET coupled to respective gates of the first set of the FET sub-devices and respective gates of the second set of the FET sub-devices.
5. The method as recited in claim 1 , further comprising forming the first set of the FET sub-devices or the second set of the FET sub-devices to couple a source of a third FET sub-device of the first set of the FET sub-devices to a drain of a fourth FET sub-device of the second set of the FET sub-devices.
6. The method as recited in claim 1 , further comprising:
forming the first set of the FET sub-devices of the integrated FET as first FinFET devices; or
forming the second set of the FET sub-devices of the integrated FET as second FinFET devices.
7. The method as recited in claim 1 , further comprising:
forming the drain terminal of the integrated FET on the substrate;
forming the source terminal of the integrated FET on the substrate; or
forming a gate terminal of the integrated FET on the substrate.
8. The method as recited in claim 1 , further comprising:
forming the first set of the FET sub-devices with at least three FET sub-devices configured to operate in saturation mode; or
forming the second set of the FET sub-devices with at least three FET sub-devices configured to operate in linear mode.
9. The method as recited in claim 1 , wherein:
the first set of the FET sub-devices is formed with respective gates that are less than 20 nanometers in length; or
the second set of the FET sub-devices is formed with respective gates that are less than 20 nanometers in length.
10. An integrated circuit comprising:
a substrate having a surface;
an integrated field-effect transistor (FET) that includes an array of FET sub-devices formed on the surface of the substrate, the array of the FET sub-devices including:
a first group of FET sub-devices having respective gates coupled to a gate terminal of the integrated FET and including a first FET sub-device having a drain coupled to a drain terminal of the integrated FET; and
a second group of FET sub-devices having respective gates coupled to the gate terminal of the integrated FET and including a second FET sub-device having a source coupled to a source terminal of the integrated FET,
wherein the array of FET sub-devices is formed on the surface of the substrate such that the second group of FET sub-devices are disposed around at least three sides of substrate area on which the first group of FET sub-devices are disposed.
11. The integrated circuit as recited in claim 10 , wherein the array of FET sub-devices is formed on the surface of the substrate such that the second group of FET sub-devices are disposed to form a perimeter around the substrate area on which the first group of FET sub-devices are disposed.
12. The integrated circuit as recited in claim 10 , wherein:
the first group of FET sub-devices of the integrated FET are configured to operate in a saturation mode or saturation region; and
the second group of FET sub-devices of the integrated FET are configured to operate in a linear mode or linear region.
13. The integrated circuit as recited in claim 10 , wherein:
the respective gates of the first group of FET sub-devices have a gate length that is less than 20 nanometers; or
the respective gates of the second group of FET sub-devices have a gate length that is less than 20 nanometers.
14. The integrated circuit as recited in claim 10 , wherein:
a source of a third FET sub-device of the first group of the FET sub-devices is coupled to a drain of a fourth FET sub-device of the second group of the FET sub-devices.
15. The integrated circuit as recited in claim 10 , wherein geometry of the FET sub-devices of the first group is substantially similar to geometry of the FET sub-devices of the second group.
16. The integrated circuit as recited in claim 10 , wherein:
functionality of the integrated FET is provided at least in part by the second group of FET sub-devices; and
the second group of the FET sub-devices are disposed adjacent to the first group of FET sub-devices without having non-functional devices disposed on the substrate between the first group of FET sub-devices and the second group of FET sub-devices.
17. The integrated circuit as recited in claim 10 , wherein:
the first group of FET sub-devices is implemented on the surface of the substrate as a first group of FinFET devices of the integrated FET; or
the second group of FET sub-devices is implemented on the surface of the substrate as a second group of FinFET devices of the integrated FET.
18. The integrated circuit as recited in claim 10 , wherein the integrated circuit is embodied in whole or part as an analog circuit, a mixed-signal circuit, a current mirror, an amplifier, a filter, an analog-to-digital converter, or a digital-to-analog converter.
19. A method comprising:
providing, via a power rail, a current to a source terminal of an integrated field-effect transistor (FET) formed by multiple FET sub-devices disposed on an area of a substrate;
forming a first group of the multiple FET sub-devices on an interior portion of the area of the substrate on which the integrated FET is formed and forming a second group of the multiple FET sub-devices formed proximate a perimeter of the area of the substrate on which the integrated FET is formed;
applying voltage to a gate terminal of the integrated FET to operate the first group of the multiple FET sub-devices in saturation mode and the second group of the FET sub-devices in linear mode; and
providing, based on the voltage applied to the gate terminal, at least a portion of the current to a drain terminal of the integrated FET via the first group and the second group of the multiple FET sub-devices of the integrated FET.
20. The method as recited in claim 19 , wherein:
respective gates of the first and second groups of the multiple FET sub-devices are coupled to the gate terminal of the integrated FET; and
applying the voltage comprises applying, via the gate terminal, the voltage to the respective gates of the first and second groups of the multiple FET sub-devices.