IP Library Granted Patent US 11,335,768
Granted Patent B2
US 11,335,768 · App. 16/377,070 · Granted May 17, 2022

Integrated high voltage capacitor

Inventor: Christopher David Ainsworth (South Wales, GB)
Assignee: Semtech Corporation
H01L28/60H01L23/585H01L23/647H01L24/32H01L24/48H01L24/85H01L25/167H01L28/20H01L31/02005H01L31/02019H01L31/107H03F3/08H01L24/05H01L24/73H01L2224/0231H01L2224/02331H01L2224/04042H01L2224/05569H01L2224/32145H01L2224/48091H01L2224/48106H01L2224/48137H01L2224/48145H01L2224/48229H01L2224/73265H01L2924/12043H01L2924/19011H01L2924/19041H01L2924/19043H03F2200/165
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Quick Facts
Patent No.
US 11,335,768
App. No.
16/377,070
Granted
May 17, 2022
Kind
B2
Abstract

A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.

Claims (49)

1. A method of making an avalanche photodiode (APD)-based optical receiver with an integrated high-voltage radio frequency (RF) filter, comprising:

providing a semiconductor die including a transimpedance amplifier;

forming an integrated capacitor on the semiconductor die directly over and within a footprint of the transimpedance amplifier, wherein the integrated capacitor includes,

a first bus bar, wherein the first bus bar is electrically isolated from all components formed in the semiconductor die,

a first plurality of fingers extending from the first bus bar,

a second bus bar,

a second plurality of fingers extending from the second bus bar, wherein the second plurality of fingers is interleaved with the first plurality of fingers within a first conductive layer with a horizontal spacing of approximately 0.3 micrometers (μm) between individual fingers of the first plurality of fingers and second plurality of fingers,

a third bus bar formed over the first bus bar,

a third plurality of fingers extending from the third bus bar, wherein each finger of the third plurality of fingers is aligned directly over a respective finger of the first plurality of fingers,

a fourth bus bar formed over the second bus bar,

a fourth plurality of fingers extending from the fourth bus bar, wherein each finger of the fourth plurality of fingers is aligned directly over a respective finger of the second plurality of fingers,

a first conductive via extending from the first bus bar to the third bus bar, and

a second conductive via extending from the second bus bar to the fourth bus bar;

forming an integrated resistor over the semiconductor die, wherein the integrated resistor and integrated capacitor form a radio frequency (RF) filter;

disposing the semiconductor die into a can-shaped package;

disposing an avalanche photodiode (APD) on the semiconductor die with a cathode of the APD coupled to a circuit node between the integrated capacitor and the integrated resistor;

disposing a lens in an opening of the can-shaped package, wherein the can-shaped package is adapted to guide a fiber-optic signal through the lens and onto the APD; and

coupling the circuit node to a high voltage input of the semiconductor device, wherein the high voltage input is configured to accept a voltage of between 60 and 90 volts.

2. The method of claim 1 , further including patterning the first conductive layer to include a guard ring around the first bus bar, second bus bar, first plurality of fingers, and second plurality of fingers.

3. The method of claim 1 , further including:

providing a contact pad coupled to the integrated capacitor;

forming an insulating layer over the contact pad;

forming an opening in the insulating layer over the contact pad; and

disposing the avalanche photodiode over the opening with a conductive material between the contact pad and photodiode.

4. The method of claim 3 , further including forming a bond wire from the avalanche photodiode to the semiconductor die.

5. A method of making an optical receiver, comprising:

providing a semiconductor die including a transimpedance amplifier;

forming an integrated capacitor over the semiconductor die, wherein the integrated capacitor includes a plurality of interdigitated fingers with a finger spacing of 0.3 μm or greater between individual fingers of the plurality of interdigitated fingers;

forming an integrated resistor over the semiconductor die, wherein the integrated resistor and integrated capacitor form a radio frequency (RF) filter;

disposing the semiconductor die into a can-shaped package;

disposing an avalanche photodiode (APD) over the semiconductor die with a cathode of the APD coupled to a circuit node between the integrated capacitor and the integrated resistor and an anode of the APD coupled to the transimpedance amplifier;

disposing a lens in an opening of the can-shaped package, wherein the can-shaped package is adapted to guide a fiber-optic signal through the lens and onto the APD; and

coupling the circuit node to a high voltage node, wherein the high voltage node is configured to operate at a voltage of 35 volts or more.

6. The method of claim 5 , further including depositing a conductive epoxy between the avalanche photodiode and the semiconductor die.

7. The method of claim 5 , wherein the plurality of interdigitated fingers are vertically aligned with each other by common polarity.

8. The method of claim 7 , further including a plurality of conductive vias disposed between the plurality of interdigitated fingers.

9. The method of claim 5 , further including forming a guard ring around the integrated capacitor.

10. The method of claim 5 , wherein the integrated capacitor includes a first terminal that is electrically isolated from all components formed in the semiconductor die.

11. A method of making a semiconductor device, comprising:

providing a semiconductor die comprising a transimpedance amplifier;

forming a high voltage integrated capacitor on the semiconductor die, wherein the high voltage integrated capacitor includes a plurality of interdigitated fingers with a finger spacing of 0.3 μm or greater between individual fingers of the plurality of interdigitated fingers;

forming an integrated resistor over the semiconductor die, wherein the integrated resistor and the high voltage integrated capacitor form a radio frequency (RF) filter; and

disposing an avalanche photodiode (APD) over the semiconductor die with a cathode of the APD coupled to a circuit node between the high voltage integrated capacitor and the integrated resistor and an anode of the APD coupled to the transimpedance amplifier.

12. The method of claim 11 , further including forming the high voltage integrated capacitor by forming a first conductive layer comprising a first portion of the plurality of interdigitated fingers.

13. The method of claim 12 , further including forming the high voltage integrated capacitor by forming a second conductive layer comprising a second portion of the plurality of interdigitated fingers over the first conductive layer.

14. The method of claim 13 , further including forming the high voltage integrated capacitor by forming a conductive via between a first finger of the first portion of the plurality of interdigitated fingers and a second finger of the second portion of the plurality of interdigitated fingers.

15. The method of claim 11 , further including coupling the high voltage integrated capacitor to receive a high voltage signal through the integrated resistor, wherein the high voltage signal is between 60 and 90 volts.

16. The method of claim 11 , further including depositing a conductive epoxy or solder between the semiconductor die and avalanche photodiode.

17. The method of claim 11 , wherein the integrated capacitor includes a first terminal that is electrically isolated from all components formed in the semiconductor die.

Assignments (3)
ASSIGNMENT OF PATENT SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (049894/0523) Recorded Feb 17, 2023
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS RESIGNING AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 062784/0040 →
SECURITY INTEREST Recorded Jul 29, 2019
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 049894/0523 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2019
From: AINSWORTH, CHRISTOPHER DAVID
To: SEMTECH CORPORATION
Reel/Frame 048812/0450 →
Continuity (2)
Provisional Application 62658073 · Apr 16, 2018
Related Publication 20190319086A1 · Oct 17, 2019
Cited By (1)
US 12,237,867