Method and system for monolithic integration of photonics and electronics in CMOS processes
Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses. The devices may be fabricated on semiconductor-on-insulator (SOI) wafers utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.
1. A method comprising:
receiving an optical signal in a photonic device;
generating first modulated optical signals in the photonic device using the received optical signal;
receiving second modulated optical signals in the photonic device;
generating electrical signals based on the first and second modulated optical signals; and
communicating the electrical signals from the photonic device to an electrical device defined on a different silicon die from the photonic device using through-silicon vias.
2. The method according to claim 1 , wherein the through-silicon vias are coupled by metal contacts.
3. The method according to claim 2 , wherein the metal contacts comprise back-end metals from a CMOS process.
4. The method according to claim 1 , wherein wherein the electrical device and the photonic device are fabricated on Silicon On Insulator (SOI) wafers having different thicknesses, wherein the SOI wafers are diced to form the different silicon die and a given die on which the photonic device is fabricated.
5. The method according to claim 4 , wherein the photonic device comprises cladding layers that are fabricated using one or more oxygen implants into the given die.
6. The method according to claim 4 , wherein the photonic device comprises cladding layers that comprise a CMOS trench oxide on the given die.
7. The method according to claim 6 , wherein silicon material for the photonic device is deposited on the CMOS trench oxide using epitaxial lateral overgrowth.
8. The method according to claim 4 , wherein the photonic device comprises cladding layers that are located in selective backside etched regions of the given die below the photonic device.
9. The method according to claim 8 , further comprising reflecting optical signals using reflective surfaces in the photonic device, wherein the reflective surfaces comprise metal layers in the selective backside etched regions of the given die.
10. The method according to claim 8 , wherein silicon dioxide is integrated in the given die using oxygen implants and acts as an etch stop layer for backside etching.
11. A system comprising:
an electrical device included in a first complementary metal-oxide semiconductor (CMOS) die;
a photonic device included on a first side of a second CMOS die that is connected on a second side of the second CMOS die to the electrical device via through-silicon vias;
wherein the photonic device is configured to:
generate modulated optical signals;
generate electrical signals from the modulated optical signals; and
communicate the electrical signals to the first CMOS die using the through-silicon vias.
12. The system according to claim 11 , wherein the through-silicon vias are coupled by metal contacts to the first CMOS die.
13. The system according to claim 12 , wherein the metal contacts comprise back-end metals from a CMOS process.
14. The system according to claim 11 , wherein the electrical device and the photonic device are fabricated on Silicon On Insulator (SOI) wafers of different thicknesses, wherein the SOI wafers are diced to form the first CMOS die and the second CMOS die.
15. The system according to claim 11 , wherein the photonic device comprises cladding layers that comprise one or more oxygen implant layers in the second CMOS die.
16. The system according to claim 11 , wherein the photonic device comprises cladding layers that comprise CMOS trench oxide layers in the second CMOS die.
17. The system according to claim 16 , wherein silicon material for the photonic device is deposited on the CMOS trench oxide layers via epitaxial lateral overgrowth.
18. The system according to claim 11 , wherein the photonic device comprises cladding layers that comprise selective backside etched regions of the second CMOS die below the photonic device.
19. The system according to claim 18 , wherein reflective surfaces for the photonic device comprise metal deposited on the selectively etched regions of the second CMOS die.
20. A system comprising:
a first complementary metal-oxide semiconductor (CMOS) die having a first silicon layer thickness for a photonic device; and
a second CMOS die having a second silicon layer thickness for an electronic device, bonded to the first CMOS die by metal contacts that comprise back-end metals from a CMOS process, to define an optoelectronics receiver, wherein the second silicon layer thickness is different than the first silicon layer thickness, and wherein the system is operable to:
generate a modulated optical signal in the first CMOS die;
generate electrical signals from the modulated optical signals in the first CMOS die; and
communicate the electrical signals from the first CMOS die using through-silicon vias that extend from a first surface of the first CMOS die on which the photonic device is located to a second surface opposite to the first surface of the first CMOS die.