Semiconductor device with tiered pillar and manufacturing method thereof
View Patent ↗A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.
1. A semiconductor device, comprising:
a first redistribution layer;
a first semiconductor die electrically connected to the first redistribution layer, the semiconductor die having a top surface, a bottom surface, and a side surface;
a conductive pillar peripherally beyond the side surface of the first semiconductor die, the conductive pillar comprising a first tier electrically connected to the first redistribution layer and a second tier on and electrically connected to the first tier, wherein the conductive pillar has an aspect ratio that is greater than or equal to two; and
a second redistribution layer over the top surface of the first semiconductor die and electrically connected to the second tier of the conductive pillar.
2. The semiconductor device of claim 1 , further comprising conductive interconnection structures that are electronically connected to the first redistribution layer.
3. The semiconductor device of claim 1 , wherein:
the first tier of the conductive pillar has a first width; and
the second tier of the conductive pillar has a second width that is smaller than the first width.
4. The semiconductor device of claim 1 , further comprising a second semiconductor die coupled to the second redistribution layer.
5. The semiconductor device of claim 1 , wherein the first semiconductor die comprises bumps electrically connected to bump pads of the first redistribution layer.
6. The semiconductor device of claim 5 , further comprising an underfill material that fills a region between the bottom surface of the first semiconductor die and the first redistribution layer.
7. A semiconductor device, comprising:
a first redistribution layer;
a first semiconductor die operatively coupled to the first redistribution layer via interconnection structures on a bottom surface of the first semiconductor die; and
conductive pillars about a periphery of the first semiconductor die and electrically connected to the first redistribution layer, each conductive pillar comprising stacked tiers, wherein each conductive pillar has an aspect ratio that is greater than or equal to two.
8. The semiconductor device of claim 7 , further comprising a second redistribution layer over the first semiconductor die and electrically connected to the first redistribution layer via the conductive pillars.
9. The semiconductor device of claim 8 , further comprising a second semiconductor die coupled to the second redistribution layer.
10. The semiconductor device of claim 7 , wherein the stacked tiers of each conductive pillar comprises a first tier connected to the first redistribution layer and a second tier on the first tier.
11. The semiconductor device of claim 10 , wherein the second tier of each conductive pillar comprises a width that is smaller than a width of the first tier of each conductive pillar.
12. The semiconductor device of claim 7 , further comprising conductive interconnection structures that are electronically connected to the first redistribution layer.
13. The semiconductor device of claim 7 , wherein the first semiconductor die comprises bumps electrically connected to bump pads of the first redistribution layer.
14. The semiconductor device of claim 7 , further comprising an underfill material that fills a region between the bottom surface of the first semiconductor die and the first redistribution layer.
15. A semiconductor device, comprising:
a first redistribution layer;
a first semiconductor die electrically connected to the first redistribution layer, the semiconductor die having a top surface, a bottom surface, and a side surface;
a conductive pillar peripherally beyond the side surface of the first semiconductor die, the conductive pillar comprising a first tier electrically connected to the first redistribution layer and a second tier on and electrically connected to the first tier of the pillar, wherein the conductive pillar has an aspect ratio that is greater than or equal to two; and wherein the first tier has a first width and the second tier has a second width that is smaller than the first width;
a second redistribution layer over the first semiconductor die and electrically connected to the first redistribution layer via the conductive pillar; and
a second semiconductor die coupled to the second redistribution layer.
16. The semiconductor device of claim 15 , wherein the first semiconductor die comprises bumps electrically connected to bump pads of the first redistribution layer.
17. The semiconductor device of claim 16 , further comprising an underfill material that fills a region between the bottom surface of the first semiconductor die and the first redistribution layer.