Confining filament at pillar center for memory devices
A semiconductor device with resistive memory includes a bottom electrode disposed on a base structure, the bottom electrode having a structure that tapers up from the base structure to a tip of the bottom electrode. The semiconductor device also includes sidewall spacers on the sides of the bottom electrode, an interlayer dielectric deposition (ILD) outside the sidewall spacers, and a top dielectric layer disposed over the bottom electrode, and the sidewall spacers. The semiconductor device further includes a top electrode deposited over the bottom electrode within the sidewall spacers. A filament formation region is formed at the tip of the bottom electrode.
1. A semiconductor device including resistive memory, comprising:
a bottom electrode disposed on a base structure, the bottom electrode having a structure that tapers up from the base structure to a tip of the bottom electrode;
sidewall spacers on the sides of the bottom electrode;
an interlayer dielectric (ILD) outside the sidewall spacers;
a top dielectric layer disposed over the bottom electrode and the sidewall spacers, the top dielectric layer having a conformal thickness portion that is in direct contact with at least a portion of a tapered sidewall of the bottom electrode and the tip of the bottom electrode; and
a top electrode deposited over the bottom electrode within the sidewall spacers and directly on the top dielectric layer, wherein a filament formation region is formed at the tip of the bottom electrode.
2. The semiconductor device of claim 1 , further comprising:
a second spacer layer disposed within the sidewall spacers that pinches off a lower region of the bottom electrode.
3. The semiconductor device of claim 1 , wherein the bottom electrode is centrally disposed within the sidewall spacers.
4. A semiconductor device including resistive memory, comprising:
a bottom electrode disposed on a base structure, the bottom electrode having a structure that tapers up from the base structure to a sharp tip of the bottom electrode;
sidewall spacers on sides of the bottom electrode;
an interlayer dielectric (ILD) outside the sidewall spacers;
a dielectric layer disposed over the bottom electrode, and the sidewall spacers, the dielectric layer having a conformal thickness in direct contact with a tapered portion of the bottom electrode and the tip of the bottom electrode, the dielectric layer including pathway sites through the dielectric layer for formation of a plurality of vacancies for ion transport; and
a top electrode deposited over the bottom electrode within the sidewall spacers and directly on the dielectric layer, wherein a filament formation region is formed at the sharp tip of the bottom electrode, the pathway sites extending from the filament formation region through the dielectric layer.
5. The device of claim 4 , further comprising:
a second spacer layer disposed within the sidewall spacers that pinches off a lower region of the bottom electrode.
6. The device of claim 5 , wherein the filament region is at a center of a tip of the patterned bottom electrode.
7. The device of claim 4 , wherein the bottom electrode is a ridge with one of a conical shape, an asymptotic shape or a dome shape.
8. The device of claim 4 , wherein the bottom electrode is centrally disposed within the sidewall spacers.