Ferroelectric memory and capacitor structure thereof
A selected ferroelectric memory cell of a ferroelectric memory is electrically connected to a first bit line, a second bit line, a first word line, a second word line and a plate line. The selected ferroelectric memory cell includes a first field effect transistor (“FET”), a second FET and a ferroelectric capacitor. A control terminal and a first access terminal of the first FET are electrically connected to the first word line and the first bit line, respectively. A control terminal and a first access terminal of the second FET are electrically connected to the second word line and the second bit line, respectively. A second access terminal of the first FET is electrically connected to a first capacitor electrode of the ferroelectric capacitor and a second access terminal of the second FET. A second capacitor electrode of the ferroelectric capacitor is electrically connected to the plate line.
1. A ferroelectric memory comprising a plurality of ferroelectric memory cells, a selected one of the ferroelectric memory cells being electrically connected to a first bit line, a second bit line, a first word line, a second word line and a plate line, the selected ferroelectric memory cell comprising:
a first field effect transistor comprising a control terminal, a first access terminal and a second access terminal;
a second field effect transistor comprising a control terminal, a first access terminal and a second access terminal; and
a ferroelectric capacitor comprising a first capacitor electrode, a second capacitor electrode and a dielectric layer sandwiched between the first capacitor electrode and the second capacitor electrode,
wherein the control terminal and the first access terminal of the first field effect transistor are respectively electrically connected to the first word line and the first bit line, the second access terminal of the first field effect transistor is electrically connected to the first capacitor electrode of the ferroelectric capacitor and the second access terminal of the second field effect transistor, the second capacitor electrode of the ferroelectric capacitor is electrically connected to a plate line, the control terminal and the first access terminal of the second field effect transistor are respectively electrically connected to the second word line and the second bit line,
wherein the dielectric layer is a ferroelectric layer made of a Zr 0.8x Si 0.2x Ti (1-x) O y ferroelectric material, a Zr 0.9x Si 0.1x Ti (1-x) O y ferroelectric material, a Zr 0.95x Si 0.05x Ti (1-x) O y ferroelectric material or a Ti x Zr (1-x) O y ferroelectric material doped with Al, Si, Ti or Ta, wherein x ranges from 0.25 to 0.75 and y ranges from 1.8 to 2.2.
2. The ferroelectric memory according to claim 1 , wherein the first field effect transistor and the second field effect transistor are non-ferroelectric field effect transistors.
3. The ferroelectric memory according to claim 1 , wherein the ferroelectric capacitor comprises:
the second capacitor electrode comprising a pillar structure;
the dielectric layer covering a lateral surface and a bottom surface of the second capacitor electrode, a top surface of the second capacitor electrode being exposed from an upper opening of the dielectric layer, the dielectric layer further comprising a flange, the flange neighboring with the upper opening and extending along a direction away from the second capacitor electrode; and
the first capacitor electrode covering a lateral surface and a bottom surface of the dielectric layer, the flange of the dielectric layer covering a top surface of the first capacitor electrode.
4. The ferroelectric memory according to claim 1 , wherein a doping concentration of Al, Si, Ti or Ta ranges from 1% to 15%.
5. A capacitor structure, comprising:
a second capacitor electrode comprising a pillar structure;
a dielectric layer covering a lateral surface and a bottom surface of the second capacitor electrode, a top surface of the second capacitor electrode being exposed from an upper opening of the dielectric layer, the dielectric layer further comprising a flange, the flange neighboring with the upper opening and extending along a direction away from the second capacitor electrode; and
a first capacitor electrode covering a lateral surface and a bottom surface of the dielectric layer, the flange of the dielectric layer covering a top surface of the first capacitor electrode,
wherein the dielectric layer of the capacitor structure is a ferroelectric layer or a para-ferroelectric layer,
wherein when the dielectric layer is the ferroelectric layer, the dielectric layer is made of a Zr 0.8x Si 0.2x Ti (1-x) O y ferroelectric material, a Zr 0.9x Si 0.1x Ti (1-x) O y ferroelectric material, a Zr 0.95x Si 0.05x Ti (1-x) O y ferroelectric material or a Ti x Zr (1-x) O y ferroelectric material doped with Al, Si, Ti or Ta, wherein x ranges from 0.25 to 0.75 and y ranges from 1.8 to 2.2,
wherein when the dielectric layer is the para-ferroelectric layer, the dielectric layer is made from a ferroelectric material and a para-electric material, the ferroelectric material being an Hf 0.8x Si 0.2x Zr (1-x) O y ferroelectric material, an Hf 0.9x Si 0.1x Zr (1-x) O y ferroelectric material, an Hf 0.95x Si 0.05x Zr (1-x) O y ferroelectric material or an Hf x Zr (1-x) O y ferroelectric material doped with Al, Si, Ti or Ta, wherein x ranges from 0.25 to 0.75 and y ranges from 1.8 to 2.2.
6. The capacitor structure according to claim 5 , wherein a doping concentration of Al, Si, Ti or Ta in the ferroelectric material ranges from 1% to 15%.
7. The capacitor structure according to claim 5 , wherein the para-electric material is a combination of HfO 2 films and H f0.5 Si 0.5 O 2 films.
8. A ferroelectric memory comprising a plurality of ferroelectric memory cells, a selected one of the ferroelectric memory cells being electrically connected to a first bit line, a second bit line, a first word line, a second word line and a plate line, the selected ferroelectric memory cell comprising:
a first field effect transistor comprising a control terminal, a first access terminal and a second access terminal;
a second field effect transistor comprising a control terminal, a first access terminal and a second access terminal; and
a ferroelectric capacitor comprising a first capacitor electrode, a second capacitor electrode and a dielectric layer sandwiched between the first capacitor electrode and the second capacitor electrode,
wherein the control terminal and the first access terminal of the first field effect transistor are respectively electrically connected to the first word line and the first bit line, the second access terminal of the first field effect transistor is electrically connected to the first capacitor electrode of the ferroelectric capacitor and the second access terminal of the second field effect transistor, the second capacitor electrode of the ferroelectric capacitor is electrically connected to a plate line, the control terminal and the first access terminal of the second field effect transistor are respectively electrically connected to the second word line and the second bit line,
wherein the dielectric layer is a para-ferroelectric layer made from a ferroelectric material and a para-electric material, the ferroelectric material being an Hf 0.8x Si 0.2x Zr (1-x) O y ferroelectric material, an Hf 0.9x Si 0.1x Zr (1-x) O y ferroelectric material, an Hf 0.95x Si 0.05x Zr (1-x) O y ferroelectric material or an Hf x Zr (1-x) O y ferroelectric material doped with Al, Si, Ti or Ta, wherein x ranges from 0.25 to 0.75 and y ranges from 1.8 to 2.2.
9. The ferroelectric memory according to claim 8 , wherein a doping concentration of Al, Si, Ti or Ta ranges from 1% to 15%.
10. The ferroelectric memory according to claim 8 , wherein the para-electric material is a combination of HfO 2 films and Hf 0.5 Si 0.5 O 2 films.