IP Library Granted Patent US 10,956,283
Granted Patent B2
US 10,956,283 · App. 16/382,999 · Granted Mar 23, 2021

Memory system capable of efficiently performing an error correction operation and operating method thereof

Inventor: Jong-Min Lee (Seoul, KR)
Assignee: SK hynix Inc.
G06F11/1471G11C16/30G06F2201/82G06F2201/84G11C16/0483
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Quick Facts
Patent No.
US 10,956,283
App. No.
16/382,999
Granted
Mar 23, 2021
Kind
B2
Abstract

A memory system includes: a memory device suitable for storing system operating information; and a controller suitable for performing a check-pointing operation whenever a background operation is to be performed, performing the background operation based on the system operating information, and performing a roll-back operation based on the system operating information stored by the check-pointing operation at a time right before the background operation is performed when an error occurs during the background operation, wherein the controller performs the roll-back operation by reflecting error information on the error into the system operating information, and performing the background operation based on the system operating information with the error information reflected therein.

Claims (33)

1. A memory system, comprising:

a memory device suitable for storing system operating information; and

a controller suitable for performing a check-pointing operation whenever a background operation is to be performed, performing the background operation based on the system operating information, and performing a roll-back operation based on the system operating information stored by the check-pointing operation at a time right before the background operation is performed when an error occurs during the background operation,

wherein the controller performs the roll-back operation by reflecting error information on the error into the system operating information, and performing the background operation based on the system operating information with the error information reflected therein.

2. The memory system of claim 1 , further comprising:

a memory suitable for storing the error information and the system operating information.

3. The memory system of claim 1 , wherein the check-pointing operation includes storing the system operating information in the memory device at the time right before the background operation is performed.

4. The memory system of claim 2 , wherein the controller stores the error information in the memory whenever an error occurs while the background operation is performed.

5. The memory system of claim 3 , wherein the controller performs the background operation based on the system operating information at the time right before the background operation is performed by loading the system operating information stored in the memory device into the memory.

6. The memory system of claim 5 , wherein the controller performs the roll-back operation by synchronizing the error information stored in the memory with the system operating information that is loaded in the memory.

7. The memory system of claim 1 , wherein the error includes a program failure.

8. The memory system of claim 1 , wherein the error includes a VCC voltage drop.

9. The memory system of claim 7 , wherein the error information includes an address of a memory block where the program failure occurs.

10. The memory system of claim 8 , wherein the error information includes an address of a word line where a program operation is performed while the VCC voltage drop occurs.

11. A method for operating a memory system, comprising:

performing a check-pointing operation whenever a background operation is to be performed;

performing the background operation based on system operating information; and

performing a roll-back operation based on the system operating information stored by the check-pointing operation at a time right before the background operation is performed when an error occurs during the background operation,

wherein the performing of the roll-back operation includes

reflecting error information on the error into the system operating information obtained by the check-pointing operation, and performing the background operation based on the system operating information with the error information reflected therein.

12. The method of claim 11 , further comprising:

storing the error information and the system operating information in a memory.

13. The method of claim 11 , wherein the check-pointing operation includes storing the system operating information in a memory device at the time right before the background operation is performed.

14. The method of claim 12 , wherein the performing of the roll-back operation further comprises

storing the error information in the memory whenever an error occurs while the background operation is performed.

15. The method of claim 13 , wherein the performing of the roll-back operation includes

performing the background operation based on the system operating information at the time before the background operation is performed by loading the system operating information stored in the memory device into the memory.

16. The method of claim 15 , wherein the performing of the roll-back operation is performed by

synchronizing the error information stored in the memory with the system operating information that is loaded in the memory.

17. The method of claim 11 , wherein the error includes a program failure.

18. The method of claim 11 , wherein the error includes a VCC voltage drop.

19. The method of claim 17 , wherein the error information includes an address of a memory block where the program failure occurs.

20. The method of claim 18 , wherein the error information includes an address of a word line where a program operation is performed while the VCC voltage drop occurs.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067335/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2019
From: LEE, JONG-MIN
To: SK HYNIX INC.
Reel/Frame 048873/0499 →