Variable read latency on a serial memory bus
Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.
1. A system, comprising:
a data bus;
a host device, comprising;
a controller configured to issue a read command and an address through the data bus and subsequently drive the data bus to a defined state for a first time period; and
a memory device, comprising;
a memory array;
a serial interface, responding to the read command and the address, configured to drive the data bus to the defined state at least before an end of the first time period, and to drive data corresponding to the address onto the data bus; and
a preamble module configured to cause the serial interface to assert a preamble pattern including a start bit, prior to the data;
wherein the host device is configured to capture the data after the preamble pattern is detected.
2. The system of claim 1 , wherein the start bit is a first bit of the preamble pattern and is in an opposite state to the defined state.
3. The system of claim 1 , wherein the host device further comprises a valid time evaluation module configured to determine an average period of time, based on the preamble pattern, that the data is valid on the data bus.
4. The system of claim 3 , wherein the host device further comprises a capture point evaluation module configured to determine an optimal capture point based on the average period of time that the data is valid on the data bus.
5. The system of claim 1 , wherein the memory array includes at least one of: FLASH memory, ferroelectric RAM, ROM, DRAM, and SDRAM.
6. The system of claim 1 , wherein the data bus includes a serial interface bus comprising at least one of: a serial peripheral interface (SPI) bus, a Burst NOR bus, and a uWire bus.
7. The system of claim 1 , wherein the system is a single data rate (SDR) implementation.
8. The system of claim 1 , wherein the system is a double data rate (DDR) implementation.
9. The system of claim 1 , wherein the preamble pattern is selected by the host device during a power-up sequence.
10. A method, comprising:
issuing a read command and an address, by a host device, to a memory device through a data bus;
driving the data bus, by the host device, to a defined state for a first time period;
accessing data in the memory device corresponding to the address;
maintaining the defined state of the data bus, by the memory device, starting before at least an end of the first time period;
asserting a preamble pattern, by the memory device, on the data bus; and
capturing the data, by the host device, on the data bus when the preamble pattern is detected.
11. The method of claim 10 , further comprising:
driving the data onto the data bus, by the memory device, after the preamble pattern.
12. The method of claim 10 , wherein the preamble pattern includes a start bit, and wherein the start bit is in a state that is opposite to the defined state.
13. The method of claim 10 , further comprising:
selecting the preamble pattern, by the host device, during a power-up sequence.
14. The method of claim 10 , further comprising:
selecting the preamble pattern, by the host device, during issuing of the read command.
15. The method of claim 10 , wherein driving the data bus to the defined state comprises implementing a variable latency period during a read operation.
16. The method of claim 15 , wherein accessing the data in the memory device is executed during the variable latency period.
17. The method of claim 10 , further comprising:
determining an average period of time by the host device, based on the preamble pattern, that the data is valid on the data bus.
18. The method of claim 17 , further comprising:
determining an optimal capture point based on the average period of time that the data is valid on the data bus.
19. The method of claim 10 , wherein the memory device includes at least one of: FLASH memory, ferroelectric RAM, ROM, DRAM, and SDRAM.
20. The method of claim 10 , wherein the data bus includes a serial interface bus comprising at least one of: a serial peripheral interface (SPI) bus, a Burst NOR bus, and a uWire bus.