IP Library Granted Patent US 11,416,282
Granted Patent B2
US 11,416,282 · App. 16/383,614 · Granted Aug 16, 2022

Configurable scheduler in a graph streaming processing system

Inventors: Satyaki Koneru (Folsom, CA); Val G. Cook (Shingle Springs, CA); Ke Yin (El Dorado Hills, CA)
Assignee: Blaize, Inc.
G06F9/4843G06F9/5027G06F2209/483
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,416,282
App. No.
16/383,614
Granted
Aug 16, 2022
Kind
B2
Abstract

Systems, apparatuses and methods are disclosed for scheduling threads comprising of code blocks in a graph streaming processor (GSP) system. One system includes a scheduler for scheduling plurality of threads, the plurality of threads includes a set of instructions operating on the graph streaming processors of GSP system. The scheduler comprises a plurality of stages where each stage is coupled to an input command buffer and an output command buffer. A portion of the scheduler is implemented in hardware and comprises of a command parser operative to interpret commands within a corresponding input command buffer, a thread generator coupled to the command parser operate to generate the plurality of threads, and a thread scheduler coupled to the thread generator for dispatching the plurality of threads for operating on the plurality of graph streaming processors.

Claims (36)

1. A graph stream processing system, comprising:

a plurality of graph streaming processors operative to process a plurality of threads, wherein each of the plurality of threads is generated from a node of a plurality of nodes organized according to a topology, each node including at least one of a plurality of code blocks, and each of the plurality of threads, include a set of instructions, 1) implement the respective code block of the corresponding node, and 2) operate on the plurality of graph streaming processors by using a set of input data and producing output data;

a memory comprising data buffers to store data associated with each of the plurality of nodes, constant buffers to store data constants required for each of the plurality of nodes, command buffers to store an index indicating a location of data in the data buffers, and a code block buffer to store the plurality of code blocks;

a scheduler comprising a plurality of stages, wherein each of the stages is coupled to an input command buffer and an output command buffer, wherein the input command buffer of each stage holds commands for the stage, and the output command buffer of each stage holds commands for a next stage of the plurality of stages;

a command parser operative to interpret commands within a corresponding input command buffer;

a thread generator coupled to the command parser operative to generate the plurality of threads;

wherein the scheduler is coupled to the thread generator and operative to dispatch the plurality of threads for operating on the plurality of graph streaming processors, with one or more threads running one or more of the plurality of code blocks on different input data and producing different output data;

wherein each stage of the scheduler is operative to interpret a command within a corresponding input command buffer and in response to the interpretation, perform the steps of: generate one or more threads of the plurality of threads, execute code blocks processing indexed data, and the scheduler dispatches the one or more threads generated from at least one of the plurality of nodes for execution;

wherein dispatching is triggered by execution of a code instruction embedded in the plurality of code blocks and updating an index to the corresponding input command buffer, the index storing location in the data buffers for receiving data by the at least one of the plurality of nodes.

2. The system of claim 1 , wherein the plurality of graph streaming processors simultaneously operates on a plurality of threads of different stages.

3. The system of claim 1 , wherein each stage of the scheduler further comprises an output command buffer allocator and initializer to manage output command buffer size and clearing of the output command buffer of the stage before scheduling a thread for processing by the plurality of graph streaming processors.

4. The system of claim 3 , wherein the output command buffer allocator and initializer further comprise an output command buffer write pointer update to update a write pointer (WP) during the clearing of the output command buffer, further the write pointer indicating a completion pointer for a next stage.

5. The system of claim 3 , wherein the plurality of graph streaming processors updates the completion pointer after completing operation on a thread.

6. The system of claim 1 , wherein the plurality of graph streaming processors operating on a thread generate write commands to update the output command buffer of each stage.

7. The system of claim 1 , wherein the plurality of graph streaming processors complete operation on at least one thread of a first stage before the thread scheduler can dispatch threads from a second stage for operation, wherein operations on the threads of the second stage start after the operations on the at least one thread of the first stage.

8. The system of claim 7 , wherein commands to generate threads for the second stage are computed by the plurality of graph streaming processors operating on the at least one of threads of the first stage.

9. The system of claim 1 , the graph streaming processor system further comprising a compiler to generate the one or more code blocks for operating on the plurality of graph streaming processors.

10. The system of claim 9 , the compiler provides input commands to initiate processing of the graph streaming processor system.

11. A method of graph steam processing, comprising:

processing, by a plurality of graph streaming processors, a plurality of threads, wherein each of the plurality of threads is generated from a node of a plurality of nodes organized according to a topology, each node including at least one of a plurality of code blocks, and each of the plurality of threads, include a set of instructions, 1) implement the respective code block of the corresponding node, and 2) operate on the plurality of graph streaming processors by using a set of input data and producing output data;

storing, by a memory, data associated with each of the plurality of nodes, wherein the memory comprises data buffers to store data associated with each of the plurality of nodes, constant buffers to store data constants required for each of the plurality of nodes, command buffers to store an index indicating a location of data in the data buffers, and a code block buffer to store the plurality of code blocks;

scheduling the plurality of threads by a scheduler, wherein the scheduler includes a plurality of stages, wherein each of the stages is coupled to an input command buffer and an output command buffer, wherein the input command buffer of each stage holds commands for the stage, and the output command buffer of each stage holds commands for a next stage of the plurality of stages;

further comprising:

interpreting, by a command parser, commands within a corresponding input command buffer;

generating, by a thread generator coupled to the command parser, one or more threads;

dispatching, by the thread scheduler, one or more threads for operating on the plurality of graph streaming processors, with each thread running one or more of the plurality of code blocks but on different input data and producing different output data;

wherein each stage of the scheduler is operative to interpret a command within a corresponding input command buffer and in response to the interpretation, perform the steps of: generate one or more threads of the plurality of threads, execute code blocks processing indexed data, and the scheduler dispatches the one or more threads generated from at least one of the plurality of nodes for execution;

wherein dispatching is triggered by execution of a code instruction embedded in the plurality of code blocks and updating an index to the corresponding input command buffer, the index storing location in the data buffers for receiving data by the at least one of the plurality of nodes.

12. The method of claim 11 , two or more stages of the plurality of stages operate simultaneously.

13. The method of claim 11 , wherein each stage of the scheduler further comprising an output command buffer allocator and initializer to manage output command buffer size and clearing of the output command buffer of the stage before scheduling a thread for processing by the plurality of graph streaming processors.

14. The method of claim 13 , wherein the output command buffer allocator and initializer further comprise an output command buffer write pointer update to update a write pointer (WP) during the clearing of output command buffer, further the write pointer indicating a completion pointer for a next stage.

15. The method of claim 13 , wherein the plurality of graph streaming processors updates the completion pointer after completing operation on a thread.

16. The method of claim 11 , wherein the plurality of graph streaming processors operating on a thread generate write commands to update the output command buffer of each stage.

17. The method of claim 11 , wherein the plurality of graph streaming processors complete operation on at least one thread of a first stage before the thread scheduler can dispatch threads from a second stage for operation, where in operations on the threads of the second stage start after the operations on the at least one thread of the first stage.

18. The method of claim 17 , wherein the commands to generate threads for the second stage is computed by the plurality of graph streaming processors operating on the at least one of threads of the first stage.

19. The system of claim 11 , the graph streaming processor system further comprising a compiler to generate the one or more code blocks for operating on the plurality of graph streaming processors.

Assignments (5)
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 064274/0743 Recorded Aug 16, 2024
From: BESS VENTURES AND ADVISORY, LLC
To: BLAIZE, INC.
Reel/Frame 068672/0220 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Oct 23, 2023
From: BLAIZE, INC.
To: BESS VENTURES AND ADVISORY, LLC; BURTECH LP LLC; FRANKLIN TEMPLETON VARIABLE INSURANCE PRODUCTS TRUST - FRANKLIN SMALL-MID CAP GROWTH VIP FUND; FRANKLIN STRATEGIC SERIES - FRANKLIN SMALL-MID CAP GROWTH FUND
Reel/Frame 065317/0902 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Jul 14, 2023
From: BLAIZE, INC.
To: BESS VENTURES AND ADVISORY, LLC
Reel/Frame 064274/0743 →
CHANGE OF NAME Recorded Feb 14, 2022
From: THINCI, INC.
To: BLAIZE, INC.
Reel/Frame 059108/0985 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2019
From: KONERU, SATYAKI; COOK, VAL G.; YIN, KE
To: THINCI, INC
Reel/Frame 048968/0099 →
Continuity (4)
Continuation In Part 16270766 · Feb 8, 2019
Continuation In Part 15164848 · May 25, 2016
Provisional Application 62166507 · May 26, 2015
Related Publication 20190235917A1 · Aug 1, 2019
Cited By (2)
US 12,547,453 US 12,547,454