IP Library Granted Patent US 10,749,476
Granted Patent B2
US 10,749,476 · App. 16/387,986 · Granted Aug 18, 2020

Control of envelope tracker PMIC

Inventors: Ilan Sutskover (Hadera, IL); Eran Segev (Tel Aviv, IL); Stephan Henzler (Munich, DE); Alexander Belitzer (Munich, DE)
Assignee: Intel IP Corporation
H03F1/0222H03F1/025H03F1/34H03F3/195H03F3/24H03F3/245H04W76/27H03F3/189H03F2200/102H03F2200/504H03F2200/507H03F2200/511H03F2200/546H03K23/005
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Quick Facts
Patent No.
US 10,749,476
App. No.
16/387,986
Granted
Aug 18, 2020
Kind
B2
Abstract

A tracker circuit configured to provide a variable supply voltage to a power amplifier (PA) circuit is disclosed. The tracker circuit includes a state machine circuit comprising a plurality of states mapped in accordance with transitions associated with a mapping scheme. In some embodiments, the plurality of states of the state machine circuit identify one or more operational modes associated with the tracker circuit, wherein at least one operational mode comprises one or more voltage levels respectively associated therewith. In some embodiments, the one or more operational modes includes at least two active operational modes. In some embodiments, a transition between the one or more operational modes of the tracker circuit is controlled by a digital selection signal received from a digital communication interface associated therewith.

Claims (29)

1. A tracker circuit configured to provide a variable supply voltage to a power amplifier (PA) circuit comprises:

a state machine circuit comprising a plurality of states mapped in accordance with transitions associated with a mapping scheme, wherein the plurality of states of the state machine circuit identify one or more operational modes associated with the tracker circuit, wherein—at least one operational mode comprises one or more voltage levels associated therewith;

wherein a transition between the one or more operational modes of the tracker circuit is controlled by a digital selection signal received from a digital communication interface associated therewith; and

wherein the transition between the one or more operational modes of the tracker circuit is defined based on mapping the one or more operational modes to trajectories comprising allowable state transitions associated with the mapping scheme.

2. The circuit of claim 1 , wherein the one or more operational modes associated with the tracker circuit further comprise at least one inactive operational mode.

3. The circuit of claim 2 , wherein the at least one inactive operational mode comprises one or more of an off mode, a standby mode and an idle mode.

4. The circuit of claim 1 , wherein the one or more operational modes comprise an envelope tracking (ET) mode.

5. The circuit of claim 1 , wherein the one or more operational modes comprise an average power tracking (APT) mode.

6. The circuit of claim 1 , wherein the one or more operational modes comprise a non-tracking mode.

7. The circuit of claim 1 , wherein the plurality of states within the state machine circuit is mapped, at least partly, based on forbidden transitions associated with the mapping scheme.

8. The circuit of claim 7 , wherein the transition between the one or more operational modes of the tracker circuit is defined based on mapping the one or more operational modes to trajectories comprising, at least partly, the forbidden state transitions associated with the mapping scheme.

9. The circuit of claim 7 , wherein the transition between the one or more operational modes of the tracker circuit is defined, at least partly, based on assigning a forbidden transition associated with the mapping scheme to a unique state associated with the one or more operational modes, wherein the forbidden transition is indicative of the transition between the one or more operational modes.

10. An apparatus for envelope tracking associated with a power amplifier (PA) circuit comprises a tracker circuit configured to:

provide a variable supply voltage to the PA circuit,

wherein the tracker circuit comprises a state machine circuit comprising a plurality of states mapped in accordance with transitions associated with a mapping scheme, wherein the plurality of states of the state machine circuit identify one or more operational modes associated with the tracker circuit, wherein the one operational mode comprises one or more voltage levels associated therewith; and

wherein a transition between the one or more operational modes of the tracker circuit is controlled by a digital selection signal received from a digital communication interface associated therewith; and

wherein the transition between the one or more operational modes of the tracker circuit is defined based on mapping the one or more operational modes to trajectories of the state machine circuit, wherein the trajectories comprises allowable state transitions associated with a mapping scheme.

11. The apparatus of claim 10 , further comprising a digital control line (DCL) circuit comprising the digital communication interface configured to provide the digital selection signal to the tracker circuit.

12. The apparatus of claim 11 , further comprising a level selector circuit configured to:

generate the digital selection signal, based on a measurement associated with the PA circuit; and

provide the digital selection signal to the DCL circuit.

13. The apparatus of claim 10 , wherein the one or more operational modes associated with the tracker circuit further comprises at least one inactive operational mode.

14. The circuit of claim 13 , wherein the at least one inactive operational mode comprises one or more of an off mode, a standby mode and an idle mode.

15. The circuit of claim 10 , wherein the one or more operational modes comprise an envelope tracking (ET) mode.

16. The circuit of claim 10 , wherein the one or more operational modes comprise an average power tracking (APT) mode.

17. The circuit of claim 10 , wherein the one or more operational modes comprise a non-tracking mode.

18. The circuit of claim 10 , wherein the plurality of states within the state machine circuit is mapped, at least partly, based on forbidden transitions associated with a mapping scheme.

19. The circuit of claim 18 , wherein the transition between the one or more operational modes of the tracker circuit is defined based on mapping the one or more operational modes to trajectories of the state machine circuit, wherein the trajectories comprises allowable state transitions or the forbidden state transitions or both, associated with the mapping scheme.

20. The circuit of claim 18 , wherein the transition between the one or more operational modes of the tracker circuit is defined, at least partly, based on assigning a forbidden transition associated with the mapping scheme to a unique states associated with the one or more operational modes, wherein the forbidden transition is indicative of the transition between the one or more operational modes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 056323/0278 →
Continuity (2)
Continuation 15866951 · Jan 10, 2018
Related Publication 20190245489A1 · Aug 8, 2019
Cited By (3)
US 12,413,147 US 12,573,993 US 12,707,396