IP Library Granted Patent US 11,018,023
Granted Patent B2
US 11,018,023 · App. 16/388,361 · Granted May 25, 2021

Defect reduction of semiconductor layers and semiconductor devices by anneal and related methods

Inventor: Ali Salih (Mesa, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L21/3245H01L21/0254H01L21/02381H01L21/02675H01L21/3228H01L29/2003H01L29/66742H01L29/7886H01L29/78681H01L21/3221
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Quick Facts
Patent No.
US 11,018,023
App. No.
16/388,361
Granted
May 25, 2021
Kind
B2
Abstract

Systems and methods of the disclosed embodiments include reducing defects in a semiconductor layer. The defects may be reduced by forming the semiconductor layer on a substrate, removing at least a portion the substrate from an underside of the semiconductor layer, and annealing the semiconductor layer to reduce the defects in the layer. The annealing includes focusing energy at the layer.

Claims (16)

1. A semiconductor device, comprising:

a semiconductor layer comprising a gallium nitride (GaN) layer or an aluminum-GaN layer, within which structural defects caused by growing the semiconductor layer on a substrate are reduced throughout the entire thickness of the semiconductor layer as a result of annealing by focused energy with at least some of the substrate removed;

a back metal directly contacting and supporting the semiconductor layer;

a drain coupled to a first surface of the semiconductor layer and connected to a first electrode; and

a source coupled to the semiconductor layer and connected to a second electrode on a second surface opposite the first surface of the semiconductor layer;

a gate coupled to the first surface of the semiconductor layer; and

wherein the drain, source, and gate are isolated from each other and provide a transistor device structure.

2. The semiconductor device of claim 1 , wherein the semiconductor layer comprises a thickness of 0.1 to 20 μm to enable breakdown voltage from a few volts to thousands of volts.

3. The semiconductor device of claim 1 , wherein the semiconductor layer comprises aluminum-GaN and the aluminum percentage is between five and fifty percent.

4. The semiconductor device of claim 1 , wherein the semiconductor layer comprises annealed GaN.

5. The semiconductor device of claim 1 , wherein the semiconductor layer further comprises a top surface more amenable to receiving epitaxial growth as a result of the annealing by focused energy.

6. The semiconductor device of claim 1 , wherein the semiconductor device further comprises additional GaN or aluminum GaN grown on the semiconductor layer after the annealing by focused energy.

7. The semiconductor device of claim 6 , wherein the semiconductor layer comprises un-annealed GaN in addition to the annealed GaN.

8. The semiconductor device of claim 1 , wherein:

the structural defects caused by growing the semiconductor layer on the substrate are reduced throughout the entire thickness of the semiconductor layer as a result of annealing by focused energy with all of the substrate removed; and

the back metal is directly contacting and supporting the entire semiconductor layer.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 050156, FRAME 0421 Recorded Aug 16, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064615/0639 →
SECURITY INTEREST Recorded Aug 23, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 050156/0421 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2019
From: SALIH, ALI
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 049062/0093 →