Multi-Ladder Digital to Analog Converter
A system (e.g., a transmitter system on chip) comprises a digital-to-analog converter configured to convert an N-bit digital signal to a corresponding analog signal, where N is an integer greater than 1. The digital-to-analog converter may comprise N bias circuits, where each of the bias circuits is configured to generate a bias current, and route the bias current based on a value of a respective one of the N bits of the N-bit digital signal. Each of the N bias circuits may comprises a resistor network and a pair of switching circuits.
1 . A system comprising:
a digital-to-analog converter configured to convert an N-bit digital signal to a corresponding analog signal, wherein:
N is an integer greater than 1;
the digital-to-analog converter comprises N bias circuits; and
each of the bias circuits is configured to:
generate a bias current; and
route the bias current based on a value of a respective bit of the N-bit digital signal.
2 . The system of claim 1 , wherein each of the N bias circuits comprises a resistor network and a pair of switching circuits.
3 . The system of claim 2 , wherein the pair of switching circuits comprises:
a first switching circuit that is open when a first bit of the N-bit digital signal is a first logic value and closed when the first bit of the N-bit digital signal is a second logic value; and
a second switching circuit that is open when the first bit of the N-bit digital signal is the second logic value and closed when the first bit of the N-bit digital signal is the first logic value.
4 . The system of claim 1 , wherein a first bias circuit of the N bias circuits comprises a resistor voltage divider coupled between a first reference voltage and a first pair of switching circuits.
5 . The system of claim 4 , wherein the first pair of switching circuits are controlled by a first bit of the N-bit digital signal.
6 . The system of claim 4 , wherein a second bias circuit of the N bias circuits comprises a resistor network coupled to the first reference voltage, a second reference voltage, and a second pair of switching circuits.
7 . The system of claim 6 , wherein the second pair of switching circuits are controlled by a second bit of the N-bit digital signal.
8 . The system of claim 1 , wherein:
the N bias circuits comprises N resistor networks; and
each of the N resistor networks is conductively coupled to each other of the N resistor networks only, if at all, through one or more traces carrying a respective one or more reference voltages.
9 . The system of claim 1 , wherein:
the N bias circuits comprises N resistor networks; and
no trace other than one or more traces carrying a respective one or more direct current reference voltages is coupled to more than one of the N resistor networks.
10 . A system comprising:
a digital-to-analog converter configured to convert an N-bit digital signal to a corresponding analog signal, wherein:
N is an integer greater than 1;
the digital-to-analog converter comprises N bias circuits, each of which generates a respective one of a plurality of bias currents which are selectively coupled to either a positive input of an operational amplifier or a negative input of an operational amplifier; and
each of the N bias circuits is conductively coupled to each other of the N bias circuits only, if at all, through one or more traces carrying one or more reference voltages.
11 . The system of claim 10 , wherein each of the N bias circuits comprises a resistor network and a pair of switching circuits.
12 . The system of claim 11 , wherein the pair of switching circuits comprises:
a first switching circuit that is open when a first bit of the N-bit digital signal is a first logic value and closed when the first bit of the N-bit digital signal is a second logic value; and
a second switching circuit that is open when the first bit of the N-bit digital signal is the second logic value and closed when the first bit of the N-bit digital signal is the first logic value.
13 . The system of claim 10 , wherein a first bias circuit of the N bias circuits comprises a resistive voltage divider coupled between a first of the one or more reference voltages and a first pair of switching circuits.
14 . The system of claim 13 , wherein the first pair of switching circuits are controlled by a first bit of the N-bit digital signal.
15 . The system of claim 13 , wherein a second bias circuit of the N bias circuits comprises a resistor network coupled to the first of the one or more reference voltages, a second of the one or more reference voltages, and a second pair of switching circuits.
16 . The system of claim 15 , wherein the second pair of switching circuits are controlled by a second bit of the N-bit digital signal.
17 . The system of claim 10 , wherein each of the N bias circuits is configured to:
generate a bias current; and
route the bias current based on a value of a respective bit of the N-bit digital signal.
18 . The system of claim 17 , wherein the bias current is routed to either a first input of a second input of an operational amplifier.