Transistor structure with depletion-mode and enhancement mode-devices
A gallium nitride transistor includes a substrate on which a source region, a drain region, a drift region and a gate region are defined. The drift region extends between the source region and the drain region. The gate region includes a combination of enhancement-mode and depletion-mode devices that are positioned across the drift region and are used together to control charge density and mobility of electrons in the drift region with a relatively low threshold voltage (V th ). Enhancement-mode devices are formed using a P-type layer disposed on the substrate and coupled to a gate electrode.
1. A transistor comprising:
a compound semiconductor substrate;
a source region formed in the substrate;
a drain region formed in the substrate and separated from the source region;
a two-dimensional electron gas (2DEG) layer formed in the substrate and extending continuously from the source region to the drain region in a first direction, and extending between a first isolation region and a second isolation region in a second direction that is perpendicular to the first direction; and
a gate region formed across the 2DEG layer and including at least one depletion-mode structure and at least one enhancement-mode structure arranged sequentially in the second direction.
2. The transistor of claim 1 wherein the at least one enhancement-mode structure includes a p-type layer.
3. The transistor of claim 2 wherein the gate region includes a plurality of depletion-mode structures and a plurality of enhancement-mode structures with each enhancement-mode structure including a separate p-type layer.
4. The transistor of claim 3 wherein the plurality of depletion-mode structures and the plurality of enhancement-mode structures are arranged across the 2DEG layer in an alternating sequence.
5. The transistor of claim 4 further comprising a gate electrode that is electrically coupled to each separate p-type layer of each enhancement-mode structure of the plurality of enhancement-mode structures, and is electrically insulated from the 2DEG layer of each depletion-mode structure of the plurality of depletion-mode structures.
6. The transistor of claim 4 further comprising a gate electrode that is electrically coupled to each separate p-type layer of each enhancement-mode structure of the plurality of enhancement-mode structures, and is electrically coupled to a drift region of the substrate of each depletion-mode structure of the plurality of depletion-mode structures forming a Schottky barrier.
7. The transistor of claim 1 wherein one or more field plates are formed over a drift region and extend from the gate region towards the drain region.
8. The transistor of claim 1 wherein a threshold voltage for the transistor is between −10 Volts and −25 Volts.
9. A transistor comprising:
a compound semiconductor substrate;
a source region formed in the substrate;
a drain region formed in the substrate and separated from the source region in a first direction;
a two dimensional electron gas (2DEG) layer extending continuously from the source region to the drain region; and
a gate region formed across the 2DEG layer and positioned between the source region and the drain region, the gate region including at least one depletion-mode device and at least one enhancement-mode device arranged sequentially in a second direction that is orthogonal to the first direction.
10. The transistor of claim 9 further comprising a gate electrode that extends across the gate region.
11. The transistor of claim 10 wherein the gate region includes a plurality of enhancement-mode devices and wherein each enhancement-mode device of the plurality of enhancement-mode devices includes a p-type layer that is coupled to the gate electrode.
12. The transistor of claim 11 wherein the gate region includes a plurality of depletion-mode devices, each depletion-mode device of the plurality of depletion-mode devices positioned in-between two enhancement-mode devices such that the plurality of depletion-mode devices and the plurality of enhancement-mode devices are arranged in an alternating pattern.
13. The transistor of claim 12 wherein the gate electrode is electrically coupled to each p-type layer of each enhancement-mode device of the plurality of enhancement-mode devices and is electrically insulated from each depletion-mode device of the plurality of depletion-mode devices by a dielectric layer.
14. The transistor of claim 12 wherein the gate electrode is electrically coupled to each p-type layer of each enhancement-mode device and is electrically coupled to each depletion-mode device to form a Schottky barrier.
15. The transistor of claim 9 wherein one or more field plates are formed over a drift region and extend from the gate region towards the drain region.
16. A compound semiconductor transistor comprising:
a substrate;
a source formed in the substrate;
a drain formed in the substrate and separated from the source along a first direction;
a two dimensional electron gas (2DEG) layer extending continuously from the source to the drain; and
a gate formed across the 2DEG layer and positioned between the source and the drain, the gate including a plurality of depletion-mode devices and a plurality of enhancement-mode devices arranged in a second direction that is orthogonal to the first direction and parallel to the substrate.
17. The transistor of claim 16 wherein each enhancement-mode device of the plurality of enhancement-mode devices includes a p-type layer.
18. The transistor of claim 17 wherein the plurality of enhancement-mode devices and the plurality of depletion-mode devices are arranged in an alternating pattern having an enhancement-mode device positioned in-between two adjacent depletion-mode devices.
19. The transistor of claim 17 further comprising a gate electrode that is electrically coupled to the p-type layer of each enhancement-mode device of the plurality of enhancement-mode devices, the gate electrode electrically coupled to the substrate in a region of each depletion-mode device of the plurality of depletion-mode devices to form a plurality of Schottky barriers.