Predictive decision feedback equalizer
A digital signal processing circuit comprises a first equalizer circuit and a second equalizer circuit. An output of the second equalizer is used as feedback to generate an equalized signal. The output of the second equalizer circuit is based on a plurality of postcursor values and a plurality of precursor values, where the precursor values are generated based on an output of the first DFE circuit, and the postcursor values are generated independently of the output of the first DFE.
1. A system comprising:
a digital signal processing circuit comprising a first equalizer circuit and a second equalizer circuit, wherein:
an output of the second equalizer circuit is used as feedback to generate an equalized signal;
the output of the second equalizer circuit is based on a plurality of postcursor values and a plurality of precursor values;
the precursor values are generated based on an output of the first equalizer circuit; and
the postcursor values are generated independently of the output of the first equalizer circuit.
2. The system of claim 1 , comprising a first subtractor circuit and a first slicer circuit, wherein:
the first subtractor circuit outputs a first difference signal based on an output of the first equalizer circuit and a first signal;
the first slicer circuit converts the first difference signal to a first binary value;
the first binary value is used as a postcursor value in the first equalizer circuit; and
the first binary value is one of the precursor values in the second equalizer circuit.
3. The system of claim 2 , wherein the first signal is an output of a third equalizer circuit.
4. The system of claim 2 , comprising a second subtractor circuit and a second slicer circuit, wherein:
the second subtractor outputs a second difference signal based on the output of the second equalizer circuit and a second signal;
the second slicer converts the second difference signal to a second binary value; and
the second binary value is one of the postcursor values in the second equalizer circuit.
5. The system of claim 4 , wherein the second signal is an output of a third equalizer circuit.
6. The system of claim 4 , wherein the first signal is an output of a third equalizer circuit and the second signal is an output of a fourth equalizer circuit.
7. The system of claim 6 , wherein the fourth equalizer circuit realizes a function that is the inverse of a function realized by the third equalizer.
8. The system of claim 4 , wherein the second signal is a result of equalization and delay of the first signal.
9. The system of claim 4 , wherein:
the first signal is a result of an equalization of an input signal; and
the second signal is a delayed version of the input signal.
10. The system of claim 1 , wherein the first equalizer circuit is a decision feedback equalizer and the second equalizer circuit is a decision feedback equalizer.
11. A method comprising:
in a digital signal processing circuit comprising a first equalizer circuit and a second equalizer circuit:
generating an equalized signal based on feedback of an output of the second equalizer, wherein the output of the second equalizer circuit is based on a plurality of postcursor values and a plurality of precursor values;
generating the precursor values based on an output of the first equalizer circuit; and
generating the postcursor values independently of the output of the first equalizer circuit.
12. The method of claim 11 , wherein the digital signal processing circuit comprises a first subtractor circuit and a first slicer circuit, and the method comprises:
outputting, by the first subtractor circuit, a first difference signal based on an output of the first equalizer circuit and a first signal;
converting, by the first slicer circuit, the first difference signal to a first binary value, wherein:
the first binary value is used as a postcursor value in the first equalizer circuit; and
the first binary value is one of the precursor values in the second equalizer circuit.
13. The method of claim 12 , wherein the digital signal processing circuit comprises a third equalizer circuit and the method comprises the third equalizer circuit outputting the first signal.
14. The method of claim 12 , wherein the digital signal processing circuit comprises a second subtractor circuit and a second slicer circuit, and the method comprises:
outputting, by the second subtractor circuit, a second difference signal based on the output of the second equalizer circuit and a second signal; and
converting, by the second slicer circuit, the second difference signal to a second binary value, wherein the second binary value is one of the postcursor values in the second equalizer circuit.
15. The method of claim 14 , wherein the digital signal processing circuit comprises a third equalizer circuit and the method comprises the third equalizer circuit outputting the second signal.
16. The method of claim 14 , wherein the digital signal processing circuit comprises a third equalizer circuit and a fourth equalizer circuit, and the method comprises:
the third equalizer circuit outputting the first signal; and
the fourth equalizer circuit outputting the second signal.
17. The method of claim 16 , wherein the fourth equalizer circuit realizes a function that is the inverse of a function realized by the third equalizer circuit.
18. The method of claim 14 , comprising equalizing and delaying, by the digital signal processing circuit, the first signal to generate the second signal.
19. The method of claim 14 , comprising:
equalizing, by the digital signal processing circuit, an input signal to generate the first signal; and
delaying, by the digital signal processing circuit, the input signal to generate the second signal.
20. The method of claim 11 , wherein the first equalizer circuit is a decision feedback equalizer and the second equalizer circuit is a decision feedback equalizer.