Semiconductor memory device

1. A semiconductor memory device, comprising:

a first chip; and

a second chip,

the first chip including

a first semiconductor substrate having a first main surface extending in a first direction and a second direction, the second direction crossing the first direction,

a stacked body provided on the first semiconductor substrate, the stacked body including a plurality of electrode films stacked to be separated from each other along a third direction, the third direction crossing the first direction and the second direction,

a semiconductor member piercing the plurality of electrode films in the third direction,

a charge storage member provided between the semiconductor member and one of the plurality of electrode films,

a first pad, and

a first contact connecting the one of the plurality of electrode films to the first pad, and

the second chip including

a second semiconductor substrate having a second main surface extending in the first direction and the second direction,

a plurality of transistors formed in the second main surface,

a second pad, and

a second contact connecting one of a source/drain of one of the transistors to the second pad, wherein

the first chip and the second chip face each other such that the first pad is connected to the second pad,

a configuration of an end portion in the first direction of the stacked body is staircase-like having a plurality of terraces, each of the plurality of terraces being formed each of electrode films and the plurality of terraces including a plurality of first terraces and a second terrace,

a second region and two first regions along the first direction are set in the end portion, the second region being disposed between the two first regions,

the plurality of first terraces is disposed in each of the first regions,

the second terrace is disposed in the second region,

a length in the first direction of the second terrace is longer than the larger period of a minimum period in the first direction of the first pads and a minimum period in the first direction of the plurality of transistors, and

a length in the first direction of one of the plurality of first terraces disposed in the first region is shorter than the larger period.

2. The device according to claim 1 , further comprising a bump connected between the first pad and the second pad.

3. The device according to claim 1 , further comprising a pillar connected between the first pad and the second pad, the pillar being conductive.

4. The device according to claim 1 , wherein the first pad contacts the second pad.

5. The device according to claim 1 , wherein the first chip further includes a bit line connected to an end in the third direction of the semiconductor member, the bit line extending in the second direction.

6. The device according to claim 1 , wherein

the first chip further includes a first insulating film formed to cover the first main surface of the first semiconductor substrate, the first pad being exposed from the first insulating film, and

the second chip further includes a second insulating film formed to cover the second main surface of the second semiconductor substrate, the second pad being exposed from the second insulating film.

7. The device according to claim 1 , wherein

in the first chip, the first contact is provided in plurality correspondingly with the electrode films, and the first pad is provided in plurality correspondingly with the first contacts, and

in the second chip, the second contact is provided in plurality correspondingly with the transistors, and the second pad is provided in plurality correspondingly with the second contacts.

8. The device according to claim 7 , wherein

the first pads are arranged in an array manner when viewed in the third direction, and

the second pads are arranged in an array manner when viewed in the third direction.

9. The device according to claim 1 , wherein

the one of the plurality of electrode films is subdivided into a plurality of band-like portions arranged along the second direction, and

the first contact is connected to a first band-like portion of the plurality of band-like portions.

10. The device according to claim 1 , wherein

the stacked body is subdivided into a plurality of band-like portions arranged along the second direction, and

a slit is formed between the band-like portions.

11. The device according to claim 1 , wherein the plurality of transistors are arranged along the second direction.

12. The device according to claim 1 , wherein

the one of the plurality of electrode films is subdivided into a plurality of band-like portions arranged along the second direction, and

the plurality of band-like portions is connected to the same transistor.

13. The device according to claim 1 , wherein

the one of the plurality of electrode films is subdivided into a plurality of band-like portions arranged along the second direction, and

the first contact is connected to some of the band-like portions.

14. The device according to claim 13 , wherein the first contact is connected to a mutually-adjacent plurality of the band-like portions and is not connected to another mutually-adjacent plurality of the band-like portions.

15. The device according to claim 1 , wherein the charge storage member includes silicon and nitrogen.

16. The device according to claim 1 , wherein the charge storage member is conductive.