IP Library › Granted Patent US 10,607,988
Granted Patent B2
US 10,607,988 · App. 16/398,501 · Granted Mar 31, 2020

Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages

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Quick Facts
Patent No.
US 10,607,988
App. No.
16/398,501
Granted
Mar 31, 2020
Kind
B2
Abstract

Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

Claims (57)

1. An apparatus, comprising:

a memory cell having two transistors and one capacitor; the two transistors being a first transistor and a second transistor; the capacitor having a first node coupled with a source/drain region of the first transistor, and having a second node coupled with a source/drain region of the second transistor; the memory cell having a first body region vertically offset from the source/drain region of the first transistor, and having a second body region vertically offset from the source/drain region of the second transistor;

a first body connection line coupling the first body region of the memory cell to a first conductive region having a first reference voltage; the first body connection line comprising a first composition; and

a second body connection line coupling the second body region of the memory cell to a second conductive region having a second reference voltage; the first body connection line comprising a second composition; the first and second compositions comprising doped semiconductor material.

2. The apparatus of claim 1 , wherein the memory cell is vertically offset from an underlying supporting substrate; and wherein the first and second transistors are vertically stacked one atop another, with the capacitor being between the vertically-stacked first and second transistors.

3. The apparatus of claim 1 , wherein the memory cell is vertically offset from an underlying supporting substrate; and wherein the first and second transistors are laterally offset relative to one another, with the capacitor being vertically-offset relative to the first and second transistors.

4. The apparatus of claim 1 , wherein the first and second conductive regions are comprised by a common conductive structure.

5. The apparatus of claim 1 , wherein the first and second reference voltages are the same as one another.

6. The apparatus of claim 1 , including a wordline coupled with the first and second transistors of the memory cell; the wordline including first and second gate regions of the first and second transistors, respectively; the first and second gate regions being proximate the first and second body regions; a segment of the wordline being between the first and second gate regions; the memory cell and wordline being over an underlying supporting substrate; the capacitor being vertically offset relative to the wordline.

7. The apparatus of claim 6 , wherein:

the first gate region of the wordline has a first upper surface and a first lower surface;

the second gate region of the wordline has a second upper surface and a second lower surface;

the segment of the wordline has a third upper surface between the first and second upper surfaces of the first and second gate regions;

the segment of the wordline has a third lower surface between the first and second lower surfaces of the first and second gate regions;

the third upper surface is substantially planar with the first and second upper surfaces; and

the third lower surface is substantially planar with the first and second lower surfaces.

8. The apparatus of claim 6 , wherein:

the capacitor is above the wordline;

the first gate region of the wordline has a first upper surface and a first lower surface;

the second gate region of the wordline has a second upper surface and a second lower surface;

the segment of the wordline has a third upper surface between the first and second upper surfaces of the first and second gate regions;

the segment of the wordline has a third lower surface between the first and second lower surfaces of the first and second gate regions;

the third upper surface is substantially planar with the first and second upper surfaces; and

the third lower surface is vertically offset relative to the first and second lower surfaces.

9. The apparatus of claim 6 , wherein:

the capacitor is below the wordline;

the first gate region of the wordline has a first upper surface and a first lower surface;

the second gate region of the wordline has a second upper surface and a second lower surface;

the segment of the wordline has a third upper surface between the first and second upper surfaces of the first and second gate regions;

the segment of said same wordline has a third lower surface between the first and second lower surfaces of the first and second gate regions;

the third upper surface is vertically offset relative to the first and second upper surfaces; and

the third lower surface is substantially planar with the first and second lower surfaces.

10. An apparatus, comprising:

a first memory cell having two transistors and one capacitor; the two transistors of the first memory cell being a first transistor and a second transistor; the first transistor having first and second source/drain regions, and the second transistor having third and fourth source/drain regions; the first and second transistors being vertically-oriented such that the first and second source/drain regions are vertically offset relative to one another, and the third and fourth source/drain regions are vertically offset relative to one another; the capacitor of the first memory cell being a first capacitor; the first capacitor having a first node coupled with the first source/drain region of the first transistor, and having a second node coupled with the third source/drain region of the second transistor; the first and second nodes both comprising metal; the first memory cell having a first body region between the first and second source/drain regions of the first transistor, and having a second body region between the third and fourth source/drain regions of the second transistor;

a second memory cell having two transistors and one capacitor; the two transistors of the second memory cell being a third transistor and a fourth transistor; the third transistor having fifth and sixth source/drain regions, and the fourth transistor having seventh and eighth source/drain regions; the third and fourth transistors being vertically-oriented such that the fifth and sixth source/drain regions are vertically offset relative to one another, and the seventh and eighth source/drain regions are vertically offset relative to one another; the capacitor of the second memory cell being a second capacitor; the second capacitor having a third node coupled with the fifth source/drain region of the third transistor, and having a fourth node coupled with the seventh source/drain region of the fourth transistor; the second memory cell having a third body region between the fifth and sixth source/drain regions of the third transistor, and having a fourth body region between the seventh and eighth source/drain regions of the fourth transistor;

a first body connection line coupling the first body region of the first memory cell and the third body region of the second memory cell to a first reference voltage; and

a second body connection line coupling the second body region of the first memory cell and the fourth body region of the second memory cell to a second reference voltage.

11. The apparatus of claim 10 , wherein the first and second reference voltages are the same as one another.

12. The apparatus of claim 10 , wherein the first and second memory cells share a digit line; and wherein the digit line includes:

a first comparative bitline coupled to the second source/drain region of the first transistor and the sixth source/drain region of the third transistor; and

a second comparative bitline coupled to the fourth source/drain region of the second transistor and the eighth source/drain region of the fourth transistor.

13. The apparatus of claim 12 , wherein:

a first wordline is coupled with the first and second transistors of the first memory cell; and

a second wordline is coupled with the third and fourth transistors of the second memory cell.

14. The apparatus of claim 12 , wherein the first and second body connection lines are doped to a first conductivity type, and are spaced from the first and second comparative bitlines by spacing regions comprising semiconductor material doped to a second conductivity type different from the first conductivity type; said spacing regions comprising the second, fourth, sixth and eighth source/drain regions.

15. An apparatus, comprising:

a first memory cell having two transistors and one capacitor; the two transistors of the first memory cell being a first transistor and a second transistor; the first transistor having first and second source/drain regions, and the second transistor having third and fourth source/drain regions; the first and second transistors being vertically-oriented such that the first and second source/drain regions are vertically offset relative to one another, and the third and fourth source/drain regions are vertically offset relative to one another; the capacitor of the first memory cell being a first capacitor; the first capacitor having a first node coupled with the first source/drain region of the first transistor, and having a second node coupled with the third source/drain region of the second transistor; the first memory cell having a first body region between the first and second source/drain regions of the first transistor, and having a second body region between the third and fourth source/drain regions of the second transistor;

a second memory cell having two transistors and one capacitor; the two transistors of the second memory cell being a third transistor and a fourth transistor; the third transistor having fifth and sixth source/drain regions, and the fourth transistor having seventh and eighth source/drain regions; the third and fourth transistors being vertically-oriented such that the fifth and sixth source/drain regions are vertically offset relative to one another, and the seventh and eighth source/drain regions are vertically offset relative to one another; the capacitor of the second memory cell being a second capacitor; the second capacitor having a third node coupled with the fifth source/drain region of the third transistor, and having a fourth node coupled with the seventh source/drain region of the fourth transistor; the second memory cell having a third body region between the fifth and sixth source/drain regions of the third transistor, and having a fourth body region between the seventh and eighth source/drain regions of the fourth transistor;

the second memory cell sharing first and second comparative bitlines with the first memory cell; the first and second comparative bitlines both comprising metal;

a first body connection line coupling the first body region of the first memory cell to a first reference voltage;

a second body connection line coupling the second body region of the first memory cell to a second reference voltage;

a third body connection line coupling the third body region of the second memory cell to a third reference voltage; and

a fourth body connection line coupling the fourth body region of the second memory cell to a fourth reference voltage.

16. The apparatus of claim 15 , wherein the first and third body connection lines are substantially parallel to the first comparative bitline; wherein the second and fourth body connection lines are substantially parallel to the second comparative bitline; and wherein the first, second, third and fourth body connection lines comprise conductively-doped semiconductor material.

17. The apparatus of claim 15 , wherein the first and second comparative bitlines comprise metal.

18. The apparatus of claim 17 , wherein the first, second, third and fourth body connection lines are doped to a first conductivity type, and are spaced from the first and second comparative bitlines by spacing regions comprising semiconductor material doped to a second conductivity type different from the first conductivity type; said spacing regions comprising the second, fourth, sixth and eighth source/drain regions.

19. The apparatus of claim 15 , wherein an axis through the first and second comparative bitlines defines a mirror plane; and wherein the second memory cell is on an opposing side of the mirror plane from the first memory cell and is substantially a mirror image of the first memory cell across the mirror plane.